Abstract: Embodiments of the disclosure disclose a semiconductor device and a method manufacturing thereof. The semiconductor device includes a substrate as well as a first groove and a second groove located in the substrate, in which the second groove is formed by etching the substrate downwards from part of a bottom surface of the first groove, and a sidewall of the second groove retracts inward by a preset length relative to a sidewall of the first groove; a word layer including a first sub-portion located in the second groove and a second sub-portion located in the first groove, in which a gap is provided between a sidewall of the second sub-portion and that of the first groove; and a word line cover layer located in the first groove and covering the second sub-portion, in which an air gap structure at least located at the gap is provided in the word line cover layer.
Abstract: A method of preparing sterile human placental allografts by providing a human placental tissue from a donor within 24 hours to 72 hours post-childbirth; removing any visible blood, blood clots, and/or blood components from the human placental tissue without scraping or scrubbing the human placental tissue to preserve structural integrity of the human placental tissue; washing the human placental tissue in an isotonic solution while maintaining the structural integrity of the human placental tissue; dehydrating the human placental tissue thereby forming the dehydrated human placental tissue; resizing the dehydrated human placental tissue into dehydrated human placental tissue portions having predetermined sizes; and sterilizing the dehydrated human placental tissue portions of step (e) thereby forming the sterile human placental allograft. Also disclosed is a sterile human placental allograft produced by the method.
Abstract: A system and method for enhancing lossy compressed data. The system receives a compressed data stream, decompresses it, and enhances the decompressed data using adaptive neural network models. Key features include data characteristic analysis, dynamic model selection from multiple specialized neural networks, and quality estimation with feedback-driven optimization. The system adapts to various data types and compression levels, recovering lost information without detailed knowledge of the compression process. It implements online learning for continuous improvement and includes security measures to ensure data integrity. The method is applicable to diverse data types, including financial time-series, images, and audio.
Type:
Grant
Filed:
September 25, 2024
Date of Patent:
April 29, 2025
Assignee:
ATOMBEAM TECHNOLOGIES INC
Inventors:
Joshua Cooper, Grant Fickes, Charles Yeomans, Brian Galvin
Abstract: A multi-axis positioning stage or positioner includes a top plate supported and manipulatable by a plurality of prismatic joint actuators. Each actuator includes an actuator joint having four or five Degrees of Freedom (DOF) with the top plate. When one or more of the actuators extends or contracts, the pivot points, or four or five DOF actuator joints, of the remaining actuators are allowed to shift to move the top plate. The actuators can be disposed between at least one base plate or base structure, and can be fixed thereto.
Abstract: A system and method for planning and simulating a surgical operation to create a patient-specific spinal implant are disclosed. The system comprises a remote server configured to receive patient-specific medical image data and generate a 3D mesh model of the patient's spine using algorithms that separate vertebral bodies, remove artifacts, and smooth surfaces. A doctor's computer receives the 3D mesh model and allows real-time manipulation of intervertebral spaces to achieve a desired spinal curvature. The server generates a spinal implant design with surface-mapped endplates matching the patient's vertebral anatomy, which is transmitted to a 3D printer for manufacturing. The method includes steps of receiving image data, generating and updating the 3D mesh model based on doctor input, generating the final implant design, and transmitting it for production. The invention enables the creation of patient-specific spinal implants with improved conformity and surgical outcomes.
Abstract: Devices and methods for performing pre-analysis sample processing of biological and chemical samples using robotic liquid handlers are disclosed. Methods for solid phase extraction, protein precipitation and filtration of biological and chemical samples using automation and the devices in a rapid and convenient way are described.
Type:
Grant
Filed:
November 16, 2022
Date of Patent:
April 29, 2025
Assignee:
DPX TECHNOLOGIES, INC.
Inventors:
William E. Brewer, Kaylee R. Mastrianni
Abstract: An oscilloscope probe includes: a connector pod; a probe identification module disposed in the connector pod, the probe identification module having a cross-sectional area; and a resistor disposed in the connector pod, and in-line with the probe identification module and having a substantially identical cross-sectional area as the probe identification module.
Type:
Grant
Filed:
January 10, 2022
Date of Patent:
April 29, 2025
Assignee:
KEYSIGHT TECHNOLOGIES, INC.
Inventors:
Paul Doyle, Jeffrey John Haeffele, Stephen B. Tursich, Edward Vernon Brush
Abstract: A semiconductor structure includes: a substrate, a conductive pattern layer, a support layer and a re-distribution layer. The conductive pattern layer is arranged on the substrate. The support layer covers the conductive pattern layer and is provided with a via hole. The re-distribution layer is arranged on the support, and the re-distribution layer includes a test pad at least located in the via hole. The test pad includes a plurality of test contact portions and a plurality of recesses that are arranged alternately and connected mutually, and the recess is in corresponding contact with a portion of the conductive pattern layer in the via hole.
Abstract: An applicator for applying a medicament patch to a subject can include a top portion configured to be pressed downwards to activate an activation mechanism; a bottom portion configured to hold the medicament patch; a middle portion connected to the top portion and the bottom portion, the middle portion comprising a plurality of flex arms configured to contribute about 6-15 lbs to an activation force of the activation mechanism; a piston portion connected to the middle portion; and a compressible member positioned between the middle portion and the piston portion. When the activation mechanism is activated, the piston portion is released from the top portion and the middle portion and moves downwards via force applied by the compressible member. When the piston portion moves downwards, the medicament patch is released from the bottom portion and pushed downward by the piston portion onto a skin surface of the subject.
Type:
Application
Filed:
December 26, 2024
Publication date:
April 24, 2025
Applicant:
VAXESS TECHNOLOGIES, INC.
Inventors:
Matthew Vargas, John Spiridigliozzi, Harrison Wostein, Michael Isidoro, Logan McElhinney, Himabindu Nandivada Bailey
Abstract: Shrimp feeds and additives for preventing, reducing the occurrence of, treating, and/or facilitating recovery from white feces syndrome in shrimp. A shrimp feed additive or shrimp feed includes a phytogenic component, a nutritional component, or a combination thereof. The phytogenic component can include Quillaja saponaria, capsaicin, trans-anethole, or a combination thereof.
Type:
Application
Filed:
September 2, 2022
Publication date:
April 24, 2025
Applicant:
CAN TECHNOLOGIES, INC.
Inventors:
David A. COOK, Alejandro MAKOL ARENAS, Jose Miguel TRONCOSO, Karola WENDLER
Abstract: A storage device may maintain data reliability between sub-blocks by executing wear leveling operations such that a program-erase count (PEC) difference between sister sub-blocks is reduced. The storage device may include a memory device including blocks, and at least one of the blocks may be divided into sister sub-blocks. The storage device may also include a controller to calculate a sister sub-block threshold and process a wear leveling operation. When executing the wear leveling operation, the controller may select a destination block. The controller may also prioritize a first sister block for a multi-layer cell (MLC) flow when the PEC value of a second sister sub-block is greater than the sister sub-block threshold.
Abstract: The present disclosure relates to a method for manufacturing a semiconductor structure, the method includes: a substrate is provided; a bit line array is formed on an upper surface of the substrate, the bit line array includes several bit lines arranged at intervals, the bit lines are connected through at least one support pattern, and the at least one support pattern penetrates through the bit line array along an arrangement direction of the bit lines; a bit line side wall is formed on side walls of each of the bit lines; a part of the at least one support pattern is removed so as to expose at least one sacrificial layer; and the at least one sacrificial layer is removed, so as to form at least one air gap between the first side wall dielectric layers and the second side wall dielectric layers.
Abstract: A vehicle test system is illustrated. The vehicle test system includes a vehicle simulator comprising hardware from a vehicle to be tested. The test system further includes a controller coupled to the vehicle simulator configured to control the vehicle simulator. The test system further includes a 3D environmental simulator coupled to the vehicle simulator, wherein the 3D environmental simulator is configured simulate a 3D environment and movement of a vehicle simulated by the vehicle simulator in the 3D environment based on control inputs to devices for the vehicle simulator.
Abstract: A pulse generator, an Error Check and Scrub (ECS) circuit and a memory are provided. The pulse generator includes: a delay circuit configured to receive an ECS command signal, perform delay processing on the ECS command signal, and output a delay command signal, the delay between the ECS command signal and the delay command signal being a first preset value; and a latch circuit configured to receive the ECS command signal and the delay command signal, perform latch processing based on the ECS command signal and the delay command signal, and output an ECS pulse signal. The pulse width of the ECS command signal is provided with a plurality of values, and the pulse width of the ECS pulse signal is the first preset value.
Abstract: An overhead traveling vehicle and an overhead traveling vehicle fault processing system are provided. The overhead traveling vehicle includes: an overhead traveling vehicle main body; a main walking part, installed on the overhead traveling vehicle main body and configured to drive the overhead traveling vehicle main body to walk on tracks; an auxiliary walking part, installed on the overhead traveling vehicle main body and configured to drive the overhead traveling vehicle main body to walk on the tracks; and a control part, configured to control one of the main walking part and the auxiliary walking part to be on the tracks and to control the other one of the main walking part and the auxiliary walking part to leave the tracks.
Abstract: The disclosure relates to the technical field of semiconductors, and to a memory, a semiconductor structure and a method for same. The method includes: providing a substrate, the substrate including a plurality of conductive contact plugs in array distribution and insulation layers separating the conductive contact plugs; and forming a plurality of capacitive layers stacked and distributed in a direction perpendicular to the substrate on a surface of the substrate, each of the capacitive layers including a plurality of capacitances distributed at intervals, and the capacitances being respectively connected to different conductive contact plugs. According to the method, the storage capacity of capacitances can be increased, and product yield can be enhanced.
Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a substrate, a trench and a word line. The substrate includes an isolation structure and an active area. The active area includes irons of a first type. The trench is arranged in the active area, an inner surface of the trench includes an inversion doping layer and an oxide layer which are arranged adjacent to each other, and the inversion doping layer is arranged above the oxide layer. The word line is arranged in the trench. The inversion doping layer includes ions of a second type. The first type is contrary to the second type.
Abstract: Techniques for intelligent multi-carrier network edge application deployment are described. Traffic that is destined for an application implemented in multiple edge locations of a cloud provider network is originated by a mobile user equipment device via use of a communications network of a first communications service provider (CSP). An edge location hosting the application, from multiple such candidates, can be selected as a destination for the traffic. The edge location may be deployed in a facility of a different CSP. The traffic can be sent into the edge location using a network address of the different CSP to securely allow for its entry thereto.
Type:
Grant
Filed:
February 24, 2023
Date of Patent:
April 22, 2025
Assignee:
AMAZON TECHNOLOGIES, INC.
Inventors:
Mohammad Asif Ali Khan, Imran Adam Matin, Junaid Arif Kapadia, Amir Muhammad Rao Sultan
Inventors:
Stephen Shaffer, Jr., Frank Rodriguez, Bruce Urban, Alfred Thomas, Rajendrasinh Jadeja, Matthew McKay, Joseph Kaminkow, Marenz Ganadillo, Ariel Turgel, Daniel Harden, Elliott Ortiz, Hirotomi Teranishi