Patents Assigned to TECHNOLOGIES INC.
  • Patent number: 12283986
    Abstract: An apparatus for determining a wavelength and a power of an input signal is described. The apparatus comprises a memory which stores instructions, which when executed by the processor, cause the processor to: recover a first phase for a first Mach-Zehnder Interferometer MZI; recover a second phase for a second MZI; subtract the first phase from the second phase to provide a phase difference; determine an unwrapped phase difference as a function of wavelength; determine a coarse wavelength; and determine a first wavelength for the first FSR and a second wavelength from the second FSR; and average the first and second wavelengths to determine the wavelength of the input signal.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: April 22, 2025
    Assignee: KEYSIGHT TECHNOLOGIES, INC.
    Inventors: Marcel Zeiler, Bernd Nebendahl
  • Publication number: 20250125099
    Abstract: A serviceable energy storage device, such as a capacitor, ultracapacitor or supercapacitor, includes electrodes made from activated carbon produced from a low-cost source, such as thermal coal or another low-cost feedstock. The serviceable energy storage device includes replaceable electrolyte comprising a low-cost co-solvent and salt solution. The activated carbon is manufactured with a pore sizing selected in accordance with the electrolyte such that an electrode material pore configuration matches an ion coupling size of the electrolyte. An improved manufacturing process for the energy storage device is effective at a regular atmospheric environment, allowing the electrolyte to be subsequently replaced at the regular atmospheric environment.
    Type: Application
    Filed: December 17, 2020
    Publication date: April 17, 2025
    Applicant: ATLAS POWER TECHNOLOGIES INC.
    Inventors: Mitchell Miller, Jian Liu, Ali Khosrozadeh
  • Patent number: 12278587
    Abstract: Monitoring rotating machine position using a resolver having an input primary and one or more output secondaries magnetically coupled to the input primary. The method includes exciting the input primary with an exciter input signal, causing a first scaled version of the exciter input signal to appear in a first output secondary. Output from the first output secondary is collected. The collected output from the first output secondary is demodulated to recover gain from the input primary.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: April 15, 2025
    Assignee: L3HARRIS TECHNOLOGIES, INC.
    Inventors: Ryan W. Hinton, Daniel G. Chilinski, Kristian J. Harris
  • Patent number: 12276966
    Abstract: An industrial integrated development environment (IDE) supports the use of graphical device profiles to configure device parameters as part of an industrial control project. To allow an edit to first device represented by a first device profile to be applied easily to other device profiles, the industrial IDE system can record a user's interactions with the first device profile during a session of editing the device's parameters. These interactions are recorded as a sequence of cursor movements, mouse-click selections, keystrokes, and other such interactions. The user interactions are stored as a reusable interaction record which can be selectively applied to other device profiles to recreate or replay the user interactions on those other profiles.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: April 15, 2025
    Assignee: ROCKWELL AUTOMATION TECHNOLOGIES, INC.
    Inventors: Thomas Kazushige Sugimoto, Qin Cheng Jin, Wang Zhen
  • Patent number: 12278114
    Abstract: The present disclosure provides a manufacturing method of a semiconductor structure, including: an insulating layer includes a first dielectric layer and a second dielectric layer, a protective layer covers an upper surface of the second dielectric layer and a bottom and sidewalls of the first trench; removing part of the protective layer to expose at least part of a surface of the second dielectric layer; removing the second dielectric layer by a first wet etching process, the first wet etching process has a first etch selectivity of a material of the second dielectric layer to that of the first dielectric layer; and removing the protective layer by a second wet etching process, the second wet etching process has a second etch selectivity of a material of the protective layer to that of the first dielectric layer, and the second etch selectivity is greater than the first etch selectivity.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: April 15, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Qiang Wan, Jun Xia, Kangshu Zhan, Sen Li, Penghui Xu, Tao Liu
  • Patent number: 12275571
    Abstract: A package for containing liquid-exuding product is formed of a single sheet of film that is folded and sealed at certain locations. The package can include an active member, optionally in the form of absorbent, that is heat staked or otherwise attached to a portion of the sheet of film such that the active member is located on an interior surface of a bottom of the folded and sealed package.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: April 15, 2025
    Assignee: CSP TECHNOLOGIES, INC.
    Inventors: Neal D. Watson, Michael A. Johnston, Terrence Green
  • Patent number: 12275103
    Abstract: A welding torch assembly device comprising a revolution power connector (RPC) directly connectable to a power cable and electrically connectable to a neck of a welding torch, and a torch connector assembly for accommodating the RPC is provided. The welding torch assembly device may include an infinite rotation module with a shock sensor for allowing infinite rotation connection with a cable. The welding torch neck may be connected to the torch connector via a handnut.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: April 15, 2025
    Assignee: NASARC TECHNOLOGIES INC.
    Inventor: Nauman Basit
  • Patent number: 12277992
    Abstract: The present disclosure provides a memory device and a ZQ calibration method. The memory device includes: two calibration resistor interfaces connected to a same ZQ calibration resistor; a first master chip, a plurality of first slave chips cascaded together, a second master chip, and a plurality of second slave chips cascaded together that are all connected to the ZQ calibration resistor, where first transmission terminals and second transmission terminals are configured to transmit a ZQ flag signal; and an identification module configured to identify a priority calibration chip and a delay calibration chip, and identify the slave chip cascaded with the priority calibration chip as a primary slave chip and the slave chip cascaded with the delay calibration chip as a secondary slave chip.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: April 15, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Kai Tian
  • Patent number: 12277794
    Abstract: An input device determines presence of an actual user, instead of an artifact, by using multi-wavelength reflectance spectroscopy. Light sources are operated to illuminate an object with different colors of light at different times. A detector determines, at those different times, intensity data indicative of intensity light of these different colors as reflected from the object. The intensity data is processed to determine whether the object is part of a user or is an artifact. For example, if the object is deemed to be a user, biometric input may be acquired. The biometric input may then be processed to identify the user. The input device may be used at various locations, such as at an entry portal, point of sale, and so forth.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: April 15, 2025
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Baomin Wang, Umer Shahid, Tianyi Wang, Georgios Skolianos, Rui Zhao, Manoj Aggarwal, Gerard Guy Medioni
  • Patent number: 12277981
    Abstract: An anti-fuse cell structure includes: a first anti-fuse transistor having a first end and a second end; a first selection transistor having a first end and a second end, the first end of the first selection transistor being electrically connected to the second end of the first anti-fuse transistor; and a Blow Enable (BE) line electrically connected to a first end of the first anti-fuse transistor, and configured to perform programming operation on the first anti-fuse transistor.
    Type: Grant
    Filed: April 4, 2023
    Date of Patent: April 15, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Chuangming Hou
  • Patent number: 12277988
    Abstract: Embodiments relate to the field of semiconductor circuit design, and more particularly, to a data processing method, a data processing structure, and a memory. The data processing method includes: obtaining raw data to be stored, and grouping the raw data to obtain first split data, the first split data having equal number of code elements; encoding each of the first split data to generate first encoded data, where the first encoded data includes the first split data and check data corresponding to the first split data; reorganizing the first encoded data to generate write data; storing the write data into a memory cell; and obtaining read data in the memory cell, and decoding and checking the read data to generate corrected read data, to correct a multi-bit burst error occurring in the memory during data storage or data transmission.
    Type: Grant
    Filed: January 16, 2023
    Date of Patent: April 15, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Runjin Wu
  • Patent number: 12276965
    Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and provide a process recipe, a method and a system for generating same, and a semiconductor manufacturing method. The method for generating a diffraction-based process recipe includes: providing a basic process recipe, the basic process recipe is used to form an initial alignment pattern; and performing a feedback correction step for at least one time to adjust the basic process recipe and obtain an actual process recipe, which each time includes: obtaining a first pattern and a second pattern based on the basic process recipe prior to a current feedback correction step, the first pattern is the initial alignment pattern that is developed, the second pattern is the initial alignment pattern that is etched; and adjusting the basic process recipe prior to the current feedback correction step based on a difference between the first pattern and the second pattern.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: April 15, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shaowen Qiu
  • Patent number: 12278113
    Abstract: Embodiments of the present invention provide a method for manufacturing a semiconductor structure, which includes: a base is provided and a stack layer is formed on the base, wherein the stack layer includes at least a first sacrificial layer, and a material of the first sacrificial layer includes an amorphous elemental semiconductor material; second hard mask patterns are formed on the first sacrificial layer through a self-aligned process; a doping process is performed, which includes the operation that a region of the first sacrificial layer exposed from gaps between the second hard mask patterns is doped; the second hard mask patterns are removed; and an undoped region of the first sacrificial layer is removed through a selective etching process so as to form first sacrificial patterns.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: April 15, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Zhaohui Wang, Wentao Xu, Qiao Li
  • Patent number: 12278629
    Abstract: A delay circuit includes a self-shielding circuit and a delay. The self-shielding circuit is configured to: receive an initial command signal and N initial clock signals, register the initial command signal according to a first initial clock signal among the N initial clock signals that triggers the initial command signal at earliest, shield other N?1 second initial clock signals, and output N intermediate command signals, where N is an integer greater than or equal to 2, and the N initial clock signals have a same frequency and different phases. The delay is electrically connected to the self-shielding circuit and is configured to: receive the N intermediate command signals and the N initial clock signals, and delay and output the N intermediate command signals to obtain a delayed command signal. Thus, the accuracy of signal processing can be improved.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: April 15, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Tianchen Lu
  • Patent number: 12279060
    Abstract: A method of operating an imaging system is described. The method comprising transferring first image charges accumulated during a long exposure period of a first image frame to respective floating diffusion regions of a first pixel and a second pixel, reading out long exposure image signals from the respective floating diffusion regions to a first storage capacitor associated with the first pixel and a second storage capacitor associated with the second pixel, transferring second image charges accumulated during a short exposure period of the first image frame to the respective floating diffusion regions of the first pixel and the second pixel, reading out a short exposure image signal from a corresponding one of the floating diffusion regions to the second storage capacitor, and reading out storage charge signals from the first storage capacitor and the second storage capacitor to generate image data for the first image frame.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: April 15, 2025
    Assignee: OMNIVISION TECHNOLOGIES, INC.
    Inventor: Keiji Mabuchi
  • Patent number: 12278107
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method for forming the semiconductor structure includes: providing a base; forming a first dielectric layer on the base; then forming a plurality of first mask patterns each having zigzag shape on the first dielectric layer, in which the first mask patterns extend in a first direction; forming a plurality of second mask patterns each having zigzag shape on the first mask patterns, in which the second mask patterns extend in a second direction different from the first direction, and projections of the first mask patterns on the first dielectric layer and projections of the second mask patterns on the first dielectric layer overlap with each other to form polygons; and etching the first dielectric layer by using the second mask patterns and the first mask patterns as masks to form openings.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: April 15, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Kai Cao
  • Patent number: 12278137
    Abstract: The present disclosure provides a manufacturing method of a semiconductor structure, and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate, where a functional structure layer is formed on a surface of the substrate, and particles are provided on the surface of the functional structure layer; forming a first dielectric layer on the surface of the substrate, where the first dielectric layer covers the functional structure layer; grinding to remove part of the first dielectric layer until the particles are exposed, and removing the particles, to form first recesses on a surface of the remaining first dielectric layer; and forming a second dielectric layer on the surface of the first dielectric layer, where the second dielectric layer fills the first recesses.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: April 15, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zhugen Chu
  • Patent number: 12276972
    Abstract: The present application relates to the technical field of semiconductors, and in particular, to a wafer scheduling method and a wafer scheduling apparatus for an etching equipment. The wafer scheduling method includes: obtaining a wafer processing request, where the wafer processing request includes at least process information of wafers and an equipment processing parameter of the etching equipment; responding to the wafer processing request, and determining a wafer scheduling parameter corresponding to the process information and the equipment processing parameter, based on the process information, the equipment processing parameter, and a preset wafer scheduling policy, where the wafer scheduling parameter is used to determine a transfer time for transferring the wafers to the etching equipment for processing; and performing wafer scheduling processing on the wafers by using the wafer scheduling parameter. In this way, the wafer processing productivity of the etching equipment can be improved.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: April 15, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jianping Wang, Chien-Hung Chen, Jinjin Cao
  • Patent number: D1070995
    Type: Grant
    Filed: August 14, 2023
    Date of Patent: April 15, 2025
    Assignee: ARISTOCRAT TECHNOLOGIES, INC.
    Inventors: Rajendrasinh Jadeja, Bruce Urban
  • Patent number: D1071236
    Type: Grant
    Filed: January 25, 2023
    Date of Patent: April 15, 2025
    Assignee: PRECISION TOOL TECHNOLOGIES, INC.
    Inventors: James Gregory Goerges, Robert Lee