Patents Assigned to Tegal Corporation
  • Publication number: 20120021138
    Abstract: A NanoLayer Deposition (NLD) process for depositing composite films of tertiary, quaternary, pentanary, and hexary stoichiometric films is provided. The inventive deposition process is a cyclic process consisting of a sequence of thin film deposition and treatment steps to obtain a desired film stoichiometry. The deposition steps are not self-limiting as in atomic layer deposition. In one embodiment for depositing a compound oxide film, the deposition process comprises a first deposition, followed by a hydrogen-containing plasma treatment, a second deposition followed by a hydrogen-containing plasma treatment, and then a third deposition followed by a hydrogen-containing plasma and then an oxygen-containing plasma treatment to produce a stoichiometric quaternary film. The cyclic process is repeated until the desired overall film thickness is achieved. The inventive process is used to fabricate high k dielectric films, ferroelectric films, piezoelectric films, and other complex oxides.
    Type: Application
    Filed: September 19, 2011
    Publication date: January 26, 2012
    Applicant: TEGAL CORPORATION
    Inventors: Robert Anthony Ditizio, Tue Nguyen, Tai Dung Nguyen
  • Publication number: 20110120648
    Abstract: The present invention provides apparatus for controlling the operation of plasma etching a semiconductor substrate by an alternating etching method, the apparatus comprising: a process chamber (1) in which said substrate (2) is processed, means for generating a plasma (6); at least one first window (7) formed in a first wall (8) of said chamber (1) facing the surface (2a) to be etched of said substrate (2); at least one second window (10) formed in a second wall (11) of said chamber (1) lying in a plane different from said first wall (8); first means (18) coupled to said second window (10) to detect a light signal (17) relating to a selected wavelength emitted by said plasma (6); means (13, 15) for emitting a monochromatic light signal (14) through said first window (7) towards said surface (2a) in a direction (9) substantially perpendicular to said surface (2a) in such a manner that said incident signal (14a) is reflected on said surface (2a); second means (16) for detecting said reflected signal (14b); a
    Type: Application
    Filed: February 2, 2011
    Publication date: May 26, 2011
    Applicant: TEGAL CORPORATION
    Inventors: Michel Puech, Nicolas Launay
  • Patent number: 7867905
    Abstract: Systems and methods are disclosed to perform semiconductor processing with a process chamber; a flash lamp adapted to be repetitively triggered; and a controller coupled to the control input of the flash lamp to trigger the flash lamp. The system can deploy a solid state plasma source in parallel with the flash lamp in wafer processing.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: January 11, 2011
    Assignee: Tegal Corporation
    Inventors: Tue Nguyen, Tai Dung Nguyen, Craig Alan Bercaw
  • Publication number: 20100285237
    Abstract: A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The NLD process is a cyclic sequential deposition process, comprising introducing a first plurality of precursors to deposit a thin layer with the deposition process not self limiting, followed by introducing a second plurality of precursors for plasma treating the thin deposited layer. The plasma can be isotropic, anisotropic, or a combination of isotropic and anisotropic to optimize the effectiveness of the treatment of the thin deposited layers.
    Type: Application
    Filed: May 19, 2010
    Publication date: November 11, 2010
    Applicant: TEGAL CORPORATION
    Inventors: Robert Anthony Ditizio, Tue Nguyen, Tai Dung Nguyen
  • Publication number: 20100190353
    Abstract: A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The nanolayer deposition process is a cyclic sequential deposition process, comprising the first step of introducing a first plurality of precursors to deposit a thin film with the deposition process not self-limiting, then a second step of purging the first set of precursors and a third step of introducing a second plurality of precursors to modify the deposited thin film. The deposition step in the NLD process using the first set of precursors is not self limiting and is a function of substrate temperature and process time. The second set of precursors modifies the already deposited film characteristics. The second set of precursors can treat the deposited film such as a modification of film composition, a doping or a removal of impurities from the deposited film. The second set of precursors can also deposit another layer on the deposited film.
    Type: Application
    Filed: March 26, 2010
    Publication date: July 29, 2010
    Applicant: TEGAL CORPORATION
    Inventors: Tue Nguyen, Tai Dung Nguyen
  • Patent number: 7678705
    Abstract: An apparatus to perform semiconductor processing includes a process chamber; a plasma generator for generating a plasma in the process chamber; and a helical ribbon electrode coupled to the output of the plasma generator.
    Type: Grant
    Filed: July 5, 2001
    Date of Patent: March 16, 2010
    Assignee: Tegal Corporation
    Inventors: Tue Nguyen, Tai Dung Nguyen
  • Publication number: 20100022030
    Abstract: The present invention relates generally to semiconductor fabrication and particularly to fabricating magnetic tunnel junction devices. In particular, this invention relates to a method for using the dielectric layer in tunnel junctions as an etch stop layer to eliminate electrical shorting that can result from the patterning process.
    Type: Application
    Filed: September 2, 2009
    Publication date: January 28, 2010
    Applicant: TEGAL CORPORATION
    Inventor: Robert Anthony Ditizio
  • Patent number: 7645618
    Abstract: The present invention relates generally to semiconductor fabrication and particularly to fabricating magnetic tunnel junction devices. In particular, this invention relates to a method for using the dielectric layer in tunnel junctions as an etch stop layer to eliminate electrical shorting that can result from the patterning process.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: January 12, 2010
    Assignee: Tegal Corporation
    Inventor: Robert Anthony Ditizio
  • Publication number: 20090246385
    Abstract: A two step thin film deposition process is disclosed to provide for the simultaneous achievement of controlled stress and the achievement of preferred crystalline orientation in sputter-deposited thin films. In a preferred embodiment, a first relatively short deposition step is performed without substrate bias to establish the crystalline orientation of the deposited film followed by a second, typically relatively longer deposition step with an applied rf bias to provide for low or no stress conditions in the growing film. Sputter deposition without substrate bias has been found to provide good crystal orientation and can be influenced through the crystalline orientation of the underlying layers and through the introduction of intentionally oriented seed layers to promote preferred crystalline orientation. Conversely, sputter deposition with substrate bias has been found to provide a means for producing stress control in growing films.
    Type: Application
    Filed: March 25, 2009
    Publication date: October 1, 2009
    Applicant: TEGAL CORPORATION
    Inventors: Valery FELMETSGER, Pavel N. LAPTEV
  • Publication number: 20090242388
    Abstract: In a dual cathode magnetron, an adjustment circuit is provided between a pair of sputter targets having a coaxial (preferably frusto-conical) relationship to modify the distribution of ion and electron currents flowing from the plasma discharge to a substrate residing within a sputter chamber. A stress adjustment circuit is used to modify the ion bombardment of the growing films on the substrate resulting in a mechanism for control of the stress in the deposited films. In a preferred embodiment, the adjustment circuit comprises a variable resistor disposed between an internal shield that acts as a passive anode and a target. The value of the variable resistor influences the plasma discharge current distribution between the split sputter targets and the internal shields, and can effectively be used to adjust the properties of the deposited films.
    Type: Application
    Filed: March 25, 2009
    Publication date: October 1, 2009
    Applicant: TEGAL CORPORATION
    Inventors: Pavel N. LAPTEV, Valery FELMETSGER
  • Publication number: 20090242392
    Abstract: In a dual cathode magnetron, an adjustment circuit is provided between a pair of sputter targets having a coaxial (preferably frusto-conical) relationship to modify the distribution of ion and electron currents flowing from the plasma discharge to a substrate residing within a sputter chamber. A stress adjustment circuit is used to modify the ion bombardment of the growing films on the substrate resulting in a mechanism for control of the stress in the deposited films. In a preferred embodiment, the adjustment circuit comprises a variable resistor disposed between an internal shield that acts as a passive anode and a target. The value of the variable resistor influences the plasma discharge current distribution between the split sputter targets and the internal shields, and can effectively be used to adjust the properties of the deposited films.
    Type: Application
    Filed: March 25, 2009
    Publication date: October 1, 2009
    Applicant: Tegal Corporation
    Inventors: Pavel N. Laptev, Valery Felmetsger
  • Publication number: 20080318432
    Abstract: A reactor for processing semiconductor wafers with electrodes and other surfaces that can be one of heated, textured and/or pre-coated in order to facilitate adherence of materials deposited thereon, and eliminate the disadvantages resulting from the spaulding, flaking and/or delaminating of such materials which can interfere with semiconductor wafer processing.
    Type: Application
    Filed: September 2, 2008
    Publication date: December 25, 2008
    Applicant: TEGAL CORPORATION
    Inventors: Stephen P. DeOrnellas, Leslie G. Jerde, Kurt A. Olson
  • Patent number: 7467598
    Abstract: First and second electrodes at opposite ends and magnets between the electrodes define an enclosure. Inert gas (e.g. argon) molecules pass into the enclosure through an opening near the first electrode and from the enclosure through an opening near the second electrode. A ring near the first electrode, a plate near the second electrode and the magnets are at a reference potential (e.g. ground). The first electrode is biased at a high voltage by a high alternating voltage to produce a high intensity negative electrical field. The second electrode is biased at a low negative voltage by a low alternating voltage to produce a low intensity negative electrical field. Electrons movable in a helical path in the enclosure near the first electrode ionize inert gas molecules. A wafer having a floating potential and an insulating layer is closely spaced from the second electrode.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: December 23, 2008
    Assignee: Tegal Corporation
    Inventor: Pavel N. Laptev
  • Patent number: 7442615
    Abstract: Systems and methods are disclosed to perform semiconductor processing with a process chamber; a flash lamp adapted to be repetitively triggered; and a controller coupled to the control input of the flash lamp to trigger the flash lamp. The system can deploy a solid state plasma source in parallel with the flash lamp in wafer processing.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: October 28, 2008
    Assignee: Tegal Corporation
    Inventors: Tue Nguyen, Tai Dung Nguyen, Craig Alan Bercaw
  • Patent number: 7439188
    Abstract: A reactor for processing semiconductor wafers with electrodes and other surfaces that can be one of heated, textured and/or pre-coated in order to facilitate adherence of materials deposited thereon, and eliminate the disadvantages resulting from the spaulding, flaking and/or delaminating of such materials which can interfere with semiconductor wafer processing.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: October 21, 2008
    Assignee: Tegal Corporation
    Inventors: Stephen DeOrnellas, Leslie Jerde, Kurt Olson
  • Patent number: 7425224
    Abstract: A high pressure trapping system is provided to collect chemical vapor by-products in successive stages through chemical reasons conducted at progressively colder temperatures. A hot trap receives chemical vapor exhaust and collects a first waste, typically a solid, as a result of the high temperature completing a chemical reason in the vapor. Surviving gaseous by-products continue to the next process. The following chamber is colder, and collects waste as a solid or a liquid as a result of a chemical process dependent on the cold temperature. Sometimes a third chamber is used for even a colder chemical reaction to collect waste products. As a solid, these waste products are easier to collect, remove, and even reuse.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: September 16, 2008
    Assignee: Tegal Corporation
    Inventor: Tue Nguyen
  • Patent number: 7361387
    Abstract: A process system and a deposition method for depositing a highly controlled layered film on a workpiece is disclosed. The basic component of the apparatus is a pulsing plasma source that is capable of either exciting or not-exciting a first precursor. The pulsing plasma source includes an energy source to generate a plasma, and a plasma adjusting system to cause the plasma to either excite or not-excite a precursor. The precursor could flow continuously (an aspect totally new to ALD), or intermittently (or pulsing, standard ALD operation process). The deposition method includes the steps of pulsing the plasma to excite/not-excite the precursors and the ambient to deposit and modify the deposited layers. This procedure then can be repeated until the film reaches the desired thickness.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: April 22, 2008
    Assignee: Tegal Corporation
    Inventor: Tue Nguyen
  • Publication number: 20080083611
    Abstract: High-adhesive backside metallization may be realized when Ti is deposited with relatively low rf substrate bias power without pre-deposition rf plasma etch of the wafer. Rf induced bias voltage in the range of ?50 V to ?250 V ensured the best adhesion property of the film stack. Analysis of the interface between Ti layer and Si substrate have shown that Si diffused into Ti layer on a distance up to a depth of 10 nm, while Ti atoms penetrated about 2 nm into the Si. Hence Ti deposition with rf substrate bias enhances intermixing between Ti and Si atoms by low-energy ion bombardment without accumulation of Ar atoms in the interface area as it is inherent to metallization with pre-deposition rf plasma etch.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 10, 2008
    Applicant: TEGAL CORPORATION
    Inventor: Valery Felmetsger
  • Publication number: 20070251451
    Abstract: A process to deposit a thin film by chemical vapor deposition includes evacuating a chamber of gases; exposing a device to a gaseous first reactant, wherein the first reactant deposits on the device to form the thin film having a plurality of monolayers in thickness; evacuating the chamber of gases; exposing the device, coated with the first reactant, to a gaseous second reactant under a plasma treatment, wherein the thin film is treated by the first reactant; and repeating the previous steps.
    Type: Application
    Filed: April 24, 2007
    Publication date: November 1, 2007
    Applicant: TEGAL CORPORATION
    Inventors: Tue Nguyen, Tai Nguyen
  • Patent number: 7270729
    Abstract: First and second electrodes and magnets between the electrodes define an enclosure. The first electrode is biased at a high voltage to produce a high intensity electrical field. The second electrode is biased at a low negative voltage by a low alternating voltage to produce a low intensity electrical field. Electrons movable in a helical path in the enclosure near the first electrode ionize inert gas molecules in the enclosure. A wafer having a floating potential and an insulating layer is closely spaced from the second electrode. The second electrode and the wafer define plates of a first capacitor having a high impedance. The wafer and the inert gas ions in the enclosure define opposite plates of a second capacitor. The first capacitor accordingly controls and limits the speed at which the gas ions move to the insulating layer surface to etch this surface. The resultant etch, only a relatively few angstroms, of the insulating layer is smooth, uniform and accurate.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: September 18, 2007
    Assignee: Tegal Corporation
    Inventor: Pavel N. Laptev