Abstract: A method for containing the critical dimension growth of the feature on a semiconductor substrate includes placing a substrate with a hard mask comprised of a reactive metal or an oxidized reactive metal in a chamber and etching the wafer. The method further includes using a hard mask which has a low sputter yield and a low reactivity to the etch chemistry of the process.

Abstract: A plasma etch reactor 20 includes a reactor chamber 22 with a grounded upper electrode 24, a lower electrode 28 which is attached to a high frequency power supply 30 and a low frequency power supply 32, and a peripheral electrode 26 which is located between the upper and lower electrode, and which is allowed to have a floating potential. Rare earth magnets 46, 47 are used to establish the magnetic field which confines the plasma developed within the reactor chamber 22. The plasma etch reactor 20 is capable of etching emerging films used with high density semiconductor devices.

Abstract: A method and apparatus for minimizing or eliminating arcing or dielectric breakdown across a wafer during a semiconductor wafer processing step includes controlling the voltage across the wafer so that arcing and/or dielectric breakdown does not occur. Using an electrostatic clamp of the invention and by controlling the specific clamp voltage to within a suitable range of values, the voltage across a wafer is kept below a threshold and thus, arcing and/or dielectric breakdown is reduced or eliminated.

Abstract: Method and apparatus for etching a silicide stack including etching the silicide layer at a temperature elevated from that used to etch the rest of the layers in order to accomplish anisotropic etch.

Abstract: A reactor for processing semiconductor wafers with electrodes and other surfaces that can be one of heated, textured and/or pre-coated in order to facilitate adherence of materials deposited thereon, and eliminate the disadvantages resulting from the spaulding, flaking and/or delaminating of such materials which can interfere with semiconductor wafer processing.

Abstract: A reactor 20 includes a shield 50 which prevents the deposition of materials along a line-of-sight path from a wafer 26 toward and onto an electrode 32, or a window 38 which couples an electrode 32 to a reaction chamber of the reactor 20. The shield can be comprised of a conductor and/or an insulator. The shield can affect the character of a plasma generated in the reactor.

Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.

Abstract: A method and apparatus for minimizing or eliminating arcing or dielectric breakdown across a wafer during a semiconductor wafer processing step includes controlling the voltage across the wafer so that arcing and/or dielectric breakdown does not occur. Using an electrostatic clamp of the invention and by controlling the specific clamp voltage to within a suitable range of values, the voltage across a wafer is kept below a threshold and thus, arcing and/or dielectric breakdown is reduced or eliminated.

Abstract: A reactor 20 includes a shield 50 which prevents the deposition of materials along a line-of-sight path from a wafer 26 toward and onto an electrode 32, or a window 38 which couples an electrode 32 to a reaction chamber of the reactor 20. The shield can be comprised of a conductor and/or an insulator. The shield can affect the character of a plasma generated in the reactor.

Abstract: A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor 20 and controlling the temperature of the wafer 26 by controlling the pressure of the gas contacting the backside of the wafer 26 and/or providing a heat source 56 such as for example in the chuck 46 or electrode 28 associated with the wafer 26 in order to heat the wafer 26.

Abstract: A method for containing the critical dimension growth of the feature on a semiconductor substrate includes placing a substrate with a hard mask comprised of a reactive metal or an oxidized reactive metal in a chamber and etching the wafer. The method further includes using a hard mask which has a low sputter yield and a low reactivity to the etch chemistry of the process.

Abstract: Method and apparatus for etching a silicide stack including etching the silicide layer at a temperature elevated from that used to etch the rest of the layers in order to accomplish anisotropic etch.

Abstract: A plasma etch reactor 20 includes a reactor chamber 22 with a grounded upper electrode 24, a lower electrode 28 which is attached to a high frequency power supply 30 and a low frequency power supply 32, and a peripheral electrode 26 which is located between the upper and lower electrode, and which is allowed to have a floating potential. Rare earth magnets 46, 47 are used to establish the magnetic field which confines the plasma developed within the reactor chamber 22. The plasma etch reactor 20 is capable of etching emerging films used with high density semiconductor devices.

Abstract: A reactor 20 includes a shield 50 which prevents the deposition of materials along a line-of-sight path from a wafer 26 toward and onto an electrode 32, or a window 38 which couples an electrode 32 to a reaction chamber of the reactor 20. The shield can be comprised of a conductor and/or an insulator. The shield can affect the character of a plasma generated in the reactor.

Abstract: A reactor 20 includes a shield 50 which prevents the deposition of materials along a line-of-sight path from a wafer 26 toward and onto an electrode 32, or a window 38 which couples an electrode 32 to a reaction chamber of the reactor 20. The shield can be comprised of a conductor and/or an insulator. The shield can affect the character of a plasma generated in the reactor.

Abstract: A method and apparatus provide for etching a semiconductor wafer using a two step physical etching and a chemical etching process in order to create vertical sidewalls required for high density DRAMs and FRAMs.

Abstract: This invention relates to a plasma reactor apparatus having improved etch uniformity and throughput. Higher etch uniformity is achieved through the use of a new gas delivery mechanism and a thermally insulated wafer chuck. The vacuum insulated chuck also results in lower energy consumption and higher throughput.

Abstract: A plasma etch reactor 20 includes a reactor chamber 22 with a grounded upper electrode 24, a lower electrode 28 which is attached to a high frequency power supply 30 and a low frequency power supply 32, and a peripheral electrode 26 which is located between the upper and lower electrode, and which is allowed to have a floating potential. Rare earth magnets 46, 47 are used to establish the magnetic field which confines the plasma developed within the reactor chamber 22. The plasma etch reactor 20 is capable of etching emerging films used with high density semiconductor devices.

Abstract: A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor 20 and controlling the temperature of the wafer 26 by controlling the pressure of the gas contacting the backside of the wafer 26 and/or providing a heat source 56 such as for example in the chuck 46 or electrode 28 associated with the wafer 26 in order to heat the wafer 26.

Abstract: A reactor 20 includes a shield 50 which prevents the deposition of materials along a line-of-sight path from a wafer 26 toward and onto an electrode 32, or a window 38 which couples an electrode 32 to a reaction chamber of the reactor 20. The shield can be comprised of a conductor and/or an insulator. The shield can affect the character of a plasma generated in the reactor.