Abstract: Selected memory locations of a buffer memory having an m x n address space are loaded each with a trigger code. First and second data words, in bits and n bits respectively, are used to read the numerical value stored at a memory location of the buffer memory. If the numerical value bears a predetermined relationship to the trigger code, a predetermined response signal is generated.

Abstract: A pair of infrared linked stereoscopic glasses (18) receives a train of short infrared pulses from a transmitter (26) of a stereoscopic imaging system (10). The rising edges of the infrared pulses are synchronized with the beginnings of the even numbered fields of a stereoscopic image displayed on a video display (14). In a stereo mode, the glasses provide a three-dimensional appearance because right and left liquid crystal cells (40 and 42) switch right- and left-eye pieces (20 and 22) between transmissive and opaque states synchronously with the even and odd fields of the stereoscopic image. In a flickerless mode, the right- and left-eye pieces are both essentially continuously transmissive. An optical state controller (36) is self-synchronizing in that a single pulse of the electrical pulse train signal will control the optical states of both the right- and left-eye pieces during a complete stereoscopic image.

Abstract: A method of detecting bit errors in serial digital video uses a digital demodulator to process a parallel video data signal derived from the serial digital video. The output of the demodulator is converted to analog, lowpass filtered, squared and compared with a threshold value. The result of the comparison produces an error signal when bit errors occur. The bit errors may be counted over a predetermined time period, may be used to switch a data filter into the video data output path to conceal the bit errors, and may be used to map the bit errors to a display for visualization of the location of the errors within a video image represented by the serial digital video.

Abstract: A bright video line select display for a waveform monitor is achieved by storing a selected line from a video frame of a digital video input signal. The stored selected line is iteratively substituted for a plurality of video lines during the vertical interval of the digital video input signal. When line select mode is selected, those video lines during the vertical interval are displayed as a waveform, resulting in a brighter display of the selected video line.

Abstract: A FRU assembly (10) comprises a melt chamber (20) including multiple subchambers (30) in which sticks of phase change ink (38, 40) are inserted and melted. Melted ink flows through apertures (54) to a reservoir (28) comprising multiple compartments (56). Each compartment contains a channel (90) and a siphon plate (114) that allow a siphon action that siphons melted ink in the compartments to an orifice (100) that leads to an ink jet print head (16). Heaters (52, 82, and 142) under the control of a CPU (154) melt the ink and keep the melted ink at a desired temperature during various modes of operation.

Abstract: An improved electrode structure (42', 42") for an addressing structure using an ionizable gaseous medium has a plurality of plasma discharge channels (20') and a reference electrode (30', 30") and a row electrode (62') extending along each channel. The channels open into a plenum (118) for exhausting gases from the channels and introducing into the channels an ionizable gaseous medium at a predetermined pressure. The reference electrodes and the row electrodes enter from opposite ends of the channels, and the reference electrodes cross below the plenum. The row electrodes have an end (110) spaced from the ends (102) of the channels. The end of the row electrodes is separated from the end of the channels by a first distance (D) adequate to prevent undesirable plasma discharge while the electrode structure is operating. In a first embodiment (42') the reference electrodes have an end (112) spaced from a first perimeter seal (106).

Abstract: A sampling rate converter for converting an input digital signal, such as D2 PAL, into an output digital signal, such as D1 PAL, has a pair of polyphase filters. The input digital signal is input in parallel to the two polyphase filters, with the phase selected by one of the filters being offset by one from that of the other. The outputs of the polyphase filters are input to a linear interpolator to produce the output digital signal. The resolution of the sampling rate conversion is a function of the number of phases N of the polyphase filters and the number of interpolation steps M of the interpolator.

Abstract: A three-dimensional test signal for a video codec is generated by injecting a conventional foreground test signal at a predetermined location as a foreground component within a background test signal as a background component, the background component having a variable complexity. The three-dimensional test signal is input to the video codec and the output of the video codec is measured using conventional measurement instruments. The background component may be a pseudo-random noise signal, a zone plate signal or other variable complexity-type signal, with the foreground component occurring at greater intervals than the neighboring pixels used by the codec compression algorithm. The conventional measurement instruments display only the foreground component with distortions in the video codec caused by the complexity of the background component appearing in the display.

Abstract: An apparatus for addressing data storage elements (16) uses an ionizable gas excited by an AC energy source to store an analog datum in and read an analog datum out of each of the storage elements. The storage elements are defined by the overlapping areas of multiple column electrodes (18) extending in a common direction on a first substrate (48) and multiple channels (20) extending in a common direction on a second substrate (54). A layer of dielectric material (46) separates the first and the second substrates, which are positioned face-to-face and spaced-apart with the direction of the channels transverse to that of the column electrodes. Each of the channels is filled with an ionizable gas and includes two row electrodes electrically isolated from each other. At least one of the row electrodes is isolated from the gas by a dielectric coating (65) to prevent nonuniform current flow in certain regions along the length of a channel.

Abstract: The disclosed HBT IC process can fabricate npn heterojunction bipolar transistors, Schottky diodes, MIM capacitors, spiral inductors, and NiCr resistors. Two levels of interconnect metal are available. The first level metal is a conventional dielectric-insulated metal conductor. The second level metal includes an air-bridge for contacting the HBT emitters, which are on top of three level mesa structures. It is also an advanced low loss, low capacitance, air dielectric conductor useful for long interconnects and inductors. MIM capacitors are formed by sandwiching silicon nitride between the first layer metal and a capacitor top plate made with landed air-bridge metal. Precision thin film resistors are fabricated by depositing NiCr on silicon nitride. The three-level active mesa structure is etched down to the GaAs substrate, for lateral device isolation, with a truncated pyramidal shape which permits good step coverage of dielectric and metallization layers. The wet etching process uses a composition of H.sub.

Abstract: A method of detection of metastability of a trigger in a digital storage oscilloscope compares a predetermined address used to produce a trigger ready signal with a current address determined by the occurrence of a trigger event after the trigger ready signal. If the difference between the two addresses is within a predetermined limit, a metastable condition is indicated, and data acquired is treated as corrupted data.

Abstract: An equivalent time sampler uses an oscillator for sampling an input waveform having a repetitive component. A periodic signal is derived from the input waveform, and an offset frequency is derived from the periodic signal. The periodic signal and offset frequency are input to an offset locked oscillator to generate a sampling frequency that is the combination of the periodic signal and the offset frequency. The sampling frequency is used to obtain a sample of the input waveform for each acquisition cycle of the waveform.

Abstract: A digital architecture for a pulse generator includes a triggerable voltage controlled oscillator (VCO) with two alternative sources of frequency control voltage, an internal DAC or a phase frequency comparison with an external timebase. In a top octave of operation, the output of the triggerable VCO is used to produce output pulses whose edge locations are then adjusted by small digital increments or "slivers" and very small analog increments or "verniers". In lower octaves of operation, the contents of a pattern RAM serve to frequency divide the triggerable VCO output frequency by powers of two. The RAM contents are converted to a serial bit stream that imposes the coarse pulse width and period as an integral number of top octave periods, or quanta. The edge locations are then adjusted with slivers and verniers, as in the top octave. Automatic calibration facilities are included.

Abstract: An instrument module development system for a computer-based instrument system, which system includes a chassis with slots for receiving various instrument modules and a system bus with a conventional computer bus for conveying commands and data between a host computer and the instrument modules and with additional lines for conveying control signals and data between the various instrument modules, has a module housing for insertion into one of the chassis slots, a development board mounted therein, and a serial input/output (SI/O) board. The development board includes a conventional computer processor, ROM, and computer bus interface circuits all interconnected by an intramodule bus. Firmware in the development board ROM enables the module to communicate with the host computer through the system bus. User developed applications firmware in the development board ROM enables the processor to communicate with and control a user provided instrument board via the intramodule bus.

Abstract: A digital architecture for a pulse generator includes a triggerable voltage controlled oscillator (VCO) with two alternative sources of frequency control voltage, an internal DAC or a phase frequency comparison with an external timebase. In a top octave of operation, the output of the triggerable VCO is used to produce output pulses whose edge locations are then adjusted by small digital increments or "slivers" and very small analog increments or "verniers". In lower octaves of operation, the contents of a pattern RAM serve to frequency divide the triggerable VCO output frequency by powers of two. The RAM contents are converted to a serial bit stream that imposes the coarse pulse width and period as an integral number of top octave periods, or quanta. The edge locations are then adjusted with slivers and verniers, as in the top octave. Automatic calibration facilities are included.

Abstract: An improved circuit simulator interface permits a user to define one or more output parameters describing behavior of hierarchically-defined subcircuits of a circuit. The user defines each output parameter by a hierarchial expression including one or more primitive output parameters generated by a simulator when simulating the circuit or other user-defined output parameters describing behavior of subcircuits of the circuit. Once the circuit simulator has simulated the circuit and has generated the primitive output parameter values, the simulator interface responds to a user request to display the value of a selected user-defined output parameter by decomposing the hierarchical parameter expression defining the selected output parameter to an expression combining only primitive parameter values. The simulator interface then evaluates the decomposed expression using primitive parameter values generated by the simulator and displays the result.

Abstract: An equalized eye pattern instrument inserts an equalizer between the input of the instrument and a display device for the instrument. The equalizer compensates for losses and other distortions in a transmission path so that a digital signal at the input of the instrument may be presented to the display device in a form suitable for eye pattern display. A switch may be used to bypass the equalizer when not needed so that the input digital signal may be directly displayed. Further the equalizer is preferably adaptive so that the input digital signal may be restored to its undistorted form from the source.

Abstract: A print drum and associated clamping assembly is provided for use in printing or similar operations. The print drum is characterized by uniform thermal characteristics and is constructed from a material having thermal diffusivity of greater than about 1.3.times.10.sup.-5 m.sup.2 /sec. The print drum may moreover have a highly reflective surface that permits optical sensors to distinguish between the drum and substrate surfaces. Clamping sections of a substrate clamp assembly project through slots provided in the print drum and are raised and lowered to release and clamp a substrate respectively. Other constituents of the clamp assembly are mounted in the hollow interior of the print drum. The print drum and associated clamping mechanism is especially suitable for use in ink jet printing apparatus utilizing thermal phase change inks.

Abstract: A color processing system is provided that specifies color in a standardized, perceptually uniform color space and resolves color differences between input and/or output devices. The color processing system utilizes a color mapping techniques to adjust the results of color mapping to fit the color gamut of the output device. The color processing system may be implemented as a color rendering dictionary in a PostScript.RTM. Level 2 interpreter. An additional feature involves adaptation of PostScript.RTM. Level 1 applications to take advantage of the improved color processing system and PostScript.RTM. Level 2 flexibility.