Abstract: A data buffer includes parallel and serial data ports connected to one or more equipment modules that produce output data or respond to input commands. The data buffer also includes a serial control port communicating with a host computer. The data buffer receives and stores output data from the equipment modules via the data ports. The buffer configures each data port to match the data transfer protocol (baud rate, parity checking etc.) of the equipment module to which it is connected in response to input commands transmitted from the host computer via the control port. The host computer may also command the buffer to immediately route incoming data on one data port outward on one or more other selected data or control ports or to store incoming data for later transmission via a selected port in response to an input command. The host computer may additionally command the buffer to periodically transmit a stored data string outward on one or more designated data ports.

Abstract: An apparatus and method for digitizing a repetitive waveform using an analog oscilloscope uses a successive approximation technique. For each sample point on the repetitive waveform a digitizing level is compared with the repetitive waveform at that sample point, and the digitizing level is adjusted until it essentially equals the magnitude of the repetitive waveform at that point. The particular sample point is determined by comparing a delay level with a ramp signal that starts from an initial fixed trigger point on the repetitive waveform. Each point is digitized in this manner in one of three modes. The first mode samples the same point on successive iterations of the waveform until that point is digitized, and then the next point is digitized. The second mode samples each point once per iteration of the waveform by stepping the delay level n times during each iteration, and adjusting the digitizing level individually for each sample point until the digitization is complete.

Abstract: An analog-to-digital converter latching circuit functions alternatively in a degenerative mode and a regenerative mode. During degeneration, circuit stray capacitances are substantially discharged for resulting in fast operation. When the circuit switches from degeneration to regeneration, a small signal current is able to start the latch in the proper direction without first having to overcome charge stored in the stray capacitances.

Abstract: A multi-orifice ink jet print head array (32) includes multiple drive circuits that drive respective PZTs (16) to cause ink drops to be ejected from respective orifices (28). Each drive circuit includes a voltage divider (36) having a resistor R.sub.S. The ink drop ejection velocity is controlled by selecting an appropriate value of R.sub.S for each voltage divider, thereby compensating for imperfections in manufacturing of the print head array. The value of a particular R.sub.S is selected by temporarily connecting the corresponding voltage divider (36A), in which the value of R.sub.S is R.sub.I, to assessment circuit (56). The assessment circuit includes a potentiometer (66) with resistance value R.sub.POT. Ink drops are ejected at a rapid periodic rate as a camera (102) records the position of the ink drops with respect to a graticule (94) at the time a strobe (100) flashes. The value of R.sub.POT is adjusted until the ink drops are on the graticule as viewed on a monitor (108), at which time R.sub.POT =R.

Abstract: An active selectable digital delay circuit merges delay elements within a multiplexer to reduce power consumption, area and minimum delay. A current switch forms a basic element of a multiplexer. A group of current switches form an input to the multiplexer and another group of current switches form a control input to the multiplexer, the current switches being in a hierarchical tree configuration. Each input current switch has a resistor between an input voltage and the input to the current switch, the value of the resistor determining the amount of propagation delay between the input and output of the input current switch. With each input having a different resistance value, each input current switch provides a different amount of propagation delay for the input signal so that the delay of the output signal is determined by which input of the multiplexer is selected for output.

Abstract: A digital architecture for a pulse generator includes a triggerable voltage controlled oscillator (VCO) with two alternative sources of frequency control voltage, an internal DAC or a phase frequency comparison with an external timebase. In a top octave of operation, the output of the triggerable VCO is used to produce output pulses whose edge locations are then adjusted by small digital increments or "slivers" and very small analog increments or "verniers". In lower octaves of operation, the contents of a pattern RAM serve to frequency divide the triggerable VCO output frequency by powers of two. The RAM contents are converted to a serial bit stream that imposes the coarse pulse width and period as an integral number of top octave periods, or quanta. The edge locations are then adjusted with slivers and verniers, as in the top octave. Automatic calibration facilities are included.

Abstract: A subscriber loop tester for testing local loops of telephone switching networks has a partitioned "U" interface and an internal bus architecture for converting various transceiver circuit output data formats to a common data format. The "U" interface has a high impedance transformer meeting bandwidth and line matching requirements for different line codes and protocols for ISDN telecommunication systems. The transformer is selectively coupled to option cards each containing circuitry having AC and DC terminations matching specific line codes and protocols for ISDN telecommunications systems and other types of telecommunications systems. The option cards further contain programmable attenuators for producing a proper nominal signal level as a function of the specific line code and protocol and providing variable insertion loss. A high speed bus is selectively coupled to the option cards for coupling the formatted transceiver circuit output data between the cards and a digital bus translator.

Abstract: Error detection for digital television equipment that strips away the vertical and horizontal intervals of a digital video signal so that only the active picture portion of the digital video signal is determined by a digital test signal generated from the digital video signal. The digital test signal has replaced at a predetermined location in the active picture portion of the digital video signal one or more video data words with data values that represent check word data for the active picture portion. The check word data may be inserted into the beginning of one of the horizontal lines of the active picture portion of the next field, or may be modified and inserted into the end of the last line of the active picture portion of the same field of the digital video signal. A receiving instrument processes the output of the digital television instrument under test to generate active picture check word data.

Abstract: A dual-ranked time-interval conversion circuit. Two time trap circuits are employed to convert the time interval between a logic level transition of a first signal and a logic level transition of a second signal to an analog or digital signal representative of that time interval. Each time trap circuit employs a delay line for receiving and propagating the first signal and a series of taps and respective storage elements along the delay line for detecting and storing the logic level of the delay line at each tap at the time of receipt of a second signal. A first time trap circuit is employed to measure the time interval in course quanta of time and a second time trap circuit is employed to measure in fine quanta of time the time difference between the actual first signal-to-second signal time interval and the coarse measurement of that interval.

Abstract: A test fixture for a high pin count surface mounted IC device has a test head assembly connected to an adapter having electrically conductive elements that couple the output of the IC device to test points on the test head assembly. The test points are coupled to conductive pads on the test head assembly via conductive runs. The test head assembly conductive pads mate with conductive pad formed in the electrically conductive elements of the adapter. The conductive elements engage leads on the IC device providing conductive paths between the IC leads an the test points on the test head assembly. The test fixture is secured to the IC device by friction forces between the periphery of the IC device and the inner surface of the adapter. The test fixture or the adapter is usable as a low profile chip carrier by inverting the fixture or adapter and as a circuit board interconnect.

Abstract: An attenuator assembly (38) employs circuitry formed on an attenuator substrate (44) having short voltage divider path lengths that allow the use of low-cost divider selecting relays (58, 60, and 62) while maintaining low VSWR and aberration levels through the attenuator. An interconnect circuit board (80) provides electrical power, control signals, a ground plane shield (108), and probe coding contacts (32) for connection to the attenuator substrate. The circuits on the attenuator substrate are laser-trimmed to obtain predetermined electrical characteristics prior to assembly in a completed attenuator assembly. The attenuator substrate rests on a recess (128) formed in top margin (127) of a cavity (120) formed within a housing (42).

Abstract: A format converter for converting an input signal having a specified format to a digital signal of a pre-existing format, and for converting the digital signal back to the input signal automatically, loads an active data portion of the input signal into an input first-in/first-out (FIFO) buffer at a first data rate and reads the active data portion together with dummy filler samples from the FIFO at a second data rate as the digital signal. The number, location and/or values of the filler samples identify the specified format. In reverse the filler samples are stripped from the digital signal and the resulting active samples are loaded into an output FIFO at the second data rate. The stripped filler samples are used to determine the specified format of the original source of the data signal, and the active samples are read from the output FIFO at the first data rate in the specified format to reproduce the input signal.

Abstract: A FISO analog signal acquisition system includes a plurality of CCD arrays (20a-20d), with each array containing a plurality of CCD serial registers (22). Each serial register (22) has a first cell (23) and a large number of additional cells (24) coupled in series with the first cell (24), with acquired samples being transferred along the string of additional cells (24) according to a clock signal having two or more phases, with each CCD array (20a-20d) operating in response to a set of clock signals having a different phase (P1,P2,/P1,/P2). A tapped delay line (10), or other similar hold signal generating means, produces a plurality of closely spaced-in-time sequential hold signals in response to a master hold signal. In response to each one of the hold signals, a CMOS transistor (Q.sub.x) briefly connects an associated first cell (23) to the signal to be sampled so that a series of closely spaced-in-time samples of the signal are acquired.

Abstract: A computer terminal keyboard is sealed by a molded elastomeric top cover, shaped to conform to the housing and keys of the keyboard, and a bottom cover shaped to enclose the base of and secure the top cover around its periphery to the keyboard housing. The top cover is shaped to provide a substantially planar surface on the top plate with elevated individual key covers integrally formed in the top cover. Portitons of the top cover extending over the top face and sides of the keyboard housing are formed in a first thickness sufficient to provide a durable covering. Portions of the top cover immediately adjacent and between the individual key covers, and the sides of the key covers, are formed in a reduced, second thickness to allow for flexure as the keys are depressed. The top surface of the top cover is planar so that spilled liquid and debris are easily wiped or brushed away from around and between the key covers.

Abstract: A fixing and developing apparatus in which sheet material to be treated is passed through a high pressure nip defined by a pair of rollers. At least one of the rollers may have a composite construction. The composite roller includes an elongated tubular shell with a pressure applying external surface, an elongated core positioned within the tubular shell, and an elastomeric material disposed between the core and shell to support the shell on the core. The core may be of a number of configurations and may increase in transverse cross-sectional dimension from the respective ends of the core toward the center of the core. The core may taper continuously or in discrete steps from its center toward its first and second ends. In addition, the core may have a longitudinal cross-section with a crown in the shape of a beam deflection curve for a simply supported, uniformly constant cross-section beam. The shell may be similarly configured along its interior surface.

Abstract: Methods and apparatus for processing printed substrates having a phase change ink layer of non-uniform thickness are disclosed. Application of a combination of heat and pressure reorients the printed ink layer to provide a layer having a substantially uniform thickness and flat surface conformation, at least in the area of each discrete color. A release surface (55) is positioned adjacent the printed ink layer during processing. A resilient contact surface (56) is also provided to facilitate reorientation of the printed ink layer. Mechanical buffing of the processed, printed substrate improves image quality. Application of a light transmissive, protective coating that overlays the printed ink layer also improves image quality.

Abstract: An edge integrating phase detector for a phase locked loop passes a portion of a sync edge of an input video signal as a sampled signal to an integrator in response to a gate pulse nominally centered on a timing reference point of the sync edge. The sampled signal has a positive and negative portion. The integrator produces from the sampled signal a control signal for a VCO that is proportional to the unbalance between the positive and negative portions. The gate pulse is generated from the output of the VCO as a function of the nominal period of the input video signal.

Abstract: A high speed probe attenuator has an attenuator with a plurality of resistors connected in series between a probe input and an instrument output. A plurality of capacitors are coupled in parallel with pairs of the resistors in an interleaved fashion to spread the frequency correction along the attenuator. The output of the attenuator is coupled by a large diameter coaxial cable to a test instrument. The result is a high speed probe with no dribble-up effect and no overshoot.

Abstract: A variable transition time generator has a differential emitter follower circuit that has a push-pull signal at the inputs for driving each end of a timing capacitor. An independently variable timing current source is coupled to each end of the timing capacitor. A differential buffer amplifier passes the voltage across the timing capacitor to an output. A d.c. compensation circuit has a statically biased emitter follower pair of transistors that are driven independently by a pair of variable compensation current sources that track the independently variable timing current sources, the output of which is combined with the output of the buffer amplifier. Also combined with the output of the buffer amplifier is a step correction output derived from the differential input signal. The result is a high speed variable transition time generator that simultaneously produces independently controllable opposite polarity transitions.