Abstract: A semiconductor device is made from a body of semiconductor material having a layer of dielectric material and a first layer of conductive material over a main face of the body, the layers each having an opening therein through which an area of the main face of the body of semiconductor material is exposed. A second layer of conductive material is formed over the sides of the opening and the conductor material, whereby the second layer of conductive material is in conductive contact with the first layer of conductive material along the sides of the opening. Material of the second layer of conductive material is removed to a depth such that a portion of the main face of the body of semiconductor material is exposed but a sidewall of conductive material remains along a side of the opening and provides an electrically conductive connection between the first layer of conductive material and the body of the semiconductor material.

Abstract: A complementary composite PNP transistor includes a p-channel JFET and an operational amplifier coupled to form an ideal PNP transistor. The positive input of the operational amplifier forms the base of the composite transistor and the drain of the JFET forms the collector of the composite transistor. The anode of a diode-connected NPN transistor forms the emitter of the composite transistor, while the cathode is coupled to the source of the JFET. The diode-connected transistor provides complementary current-voltage characteristics for the composite PNP transistor since the saturation current and g.sub.m of the composite transistor are equal to that of an NPN transistor.

Abstract: A laser diode impulse circuit has a normally forward biased step recovery diode coupled to the output of a current pulse generating circuit. An inductor in parallel with a series combination of a pulse shaping network and a laser diode is coupled to the output of the step recovery diode. When the step recovery diode becomes reverse biased in response to a current pulse from the current pulse generating circuit, energy is stored in the inductor. The stored energy is then transferred from the inductor to the laser diode via the pulse shaping network to produce an optical pulse having a desired shape.

Abstract: A deformable connector provides a concentrated wiping action pressure during the connection process, yet forms a flat mating surface when it is fully mated, and that is also suitable for providing a double density connection between a printed circuit board and a flexible circuit cable, as well as other applications. The connector includes an elastomeric member whose lower surface has a first convex region at one end, a second convex region at the other end, and a concave region in a middle joining the first and second convex regions. The upper surface contains a convex region in its middle that is approximately parallel to the concave region of the lower surface, producing an approximately constant thickness over most of the length of the elastomeric member, thus forming a flat mating surface in its fully mated condition. Conductive runs to be connected to a mating surface are disposed on the lower surface of a flexible circuit or cable affixed to the lower surface of the elastomeric member.

Abstract: A method for producing a light-transmissive printed substrate is provided. The substrate is printed with a predetermined pattern of a light-transmissive phase change ink which initially transmits light in a non-rectilinear path. When the pattern of solidified phase change ink is subsequently reoriented to form an ink layer of substantially uniform thickness, a printed image layer is formed which will transmit light in a substantially rectilinear path and is suitable for overhead projection.In some instances the adhesion between the ink image layer and the substrate is not as high as is desired. This problem can result in delamination of the ink from the film under certain conditions. In order to overcome this problem, an intermediate optically clear adhesion promoting layer is introduced between the light-transmissive phase change ink and the base substrate.

Abstract: A charge-coupled device includes an array of closely spaced electrodes aligned along a lateral path on an oxide layer covering a semiconductor substrate. A portion of a channel reigon in the substate below each electrode has a tilted potential gradient providing an electrical field assisting lateral charge carrier drift within the channel region.

Abstract: An automatic trigger mask for an optical time domain reflectometer inhibits high optical level pulses in a received optical signal from saturating an optical detector in a receiver. A portion of the received optical signal is compared with a threshold signal derived from the output of the receiver. If the portion of the received optical signal exceeds the threshold signal, then a control signal is generated to open an optical switch in the optical path to the receiver so that the high optical level pulses are inhibited from reaching the optical detector.

Abstract: Stages of a graphics data processing pipeline are interconnected by a common bus for conveying data and arbitration signals to and from each stage. Each data transmitting stage arbitrates for and acquires control of the bus when it has output data to transmit to an addressable storage location within a next stage. Each pipeline stage other than a first stage generates a BUSY bit indicating whether it is processing data or awaiting new input data from its preceding stage. When one pipeline stage has output data to transmit to a next pipeline stage, the transmitting stage periodically polls the receiving stage by acquiring control of the bus and placing on the bus a particular address associated with the next stage. Whenever the next stage detects the presence of the particular address on the bus, it places its BUSY bit on the data lines of the bus.

Abstract: A method for producing a statistical profile of a repetitive electrical signal entails selecting a window pulse width that is preferably a large multiple of the period of the signal, setting a comparison threshold, and counting the time that the signal is above (or below) the comparison threshold during the window pulse. The comparison threshold is then repeatedly incremented (or decremented) over the amplitude range of the signal, while this procedure is repeated at each level. The difference is then taken between the times measured at adjacent amplitude increments and the absolute value of these differences is displayed as the waveform profile. An apparatus for implementing this method includes a counter/timer, a gate, a comparator, a pulse generation circuit, a comparison threshold generation circuit, and a microprocessor for controlling the other circuit elements and performing calculations.

Abstract: A method and apparatus for reversibly transforming color, which is selected from a gamut of colors producible by the primaries of a color display device (20), into a perceptually uniform color space. The coordinates of the color space are readily convertible into internationally accepted standards for color measurement. Also provided, is a method for transforming the color space coordinates of a selected color into the corresponding relative primary intensity levels of the display device (20).

Abstract: A method of determining estimates of fiber loss and return signal power for an optical fiber from a return signal uses a polynomial fit with data samples representing the return signal. From the polynomial fit an estimated fiber loss value is determined. The estimated return signal power is computed using a function of the estimated fiber loss value.

Abstract: A data acquisition system suitable for use in a SAR type A/D converter has a metastable sense feature capable of sensing and resolving a metastable condition in the input latch structure of a SAR in order to enable the acquisition of each bit of a digital output word within no more than two clock cycles. In one embodiment the data acquisition system includes a master latch having an input for receiving a digital input signal and a plurality of input latches wherein the inputs of the input latches are coupled together and to the output of the master latch. A sense latch is further included wherein the input of the sense latch is coupled to the output or sense node in the master latch for sensing a metastable condition with the master latch. A plurality of secondary latches is included wherein the inputs of the secondary latches are coupled together and to the output of the sense latch.

Abstract: A digital time base with differential period delay uses the difference in period between a master oscillator and a voltage controlled oscillator phase-locked to the master oscillator to achieve small time delay increments. The oscillators are used to drive respective delay generator trigger channels that have programmable counters and state machines. A first programmable counter is a clock counter to generate a lock signal to initiate a delay sequence, the lock signals from the respective channels being input to a phase detector to generate an error signal to keep the VCO phase-locked with the master oscillator. A second programmable counter is a delay counter that is controlled by a delay state machine to generate a delay signal. The delay signal is input to respective trigger state machines to generate the desired trigger signals, the duration of the trigger signals being a function of a third programmable counter.

Abstract: A triggering control circuit varies a holdoff period for one sweep cycle whereby to lock triggering to a different, selected event viewable on an oscilloscope.

Abstract: In accordance with the present invention, a heater is included on an integrated circuit, together with a circuit for controlling the heater to selectively heat the integrated circuit and control the propagation delay time of signals passing through the integrated circuit. In a specific form of the invention, the propagation delay time of signals passing through at least a portion of an integrated circuit is measured and compared with a reference propagation delay time. The heater is controlled to increase the heat it produces when the measured propagation delay time is less than the reference propagation delay time. In addition, the heater is controlled to decrease the heat it provides when the measured propagation delay time is greater than the reference propagation delay time.

Abstract: A transmission line transformer that can balance imperfectly balanced signals, and can convert a balanced input to an unbalanced output. The transformer includes two unbalanced transmission lines each having a characteristic impedance Z.sub.o. The outer conductor of each is interrupted at its midpoint and is connected to the corresponding interrupted outer conductor of the other. An input signal applied across the ends of the first line's center conductor yields a balanced outer signal across the ends of the second line's center conductor. An unbalanced output can be obtained by terminating one end of the second line with an impedance Z.sub.o.

Abstract: Print heads are formed with spaced subheads having nozzles such that all of the lines or pixel rows on a print medium such as a sheet of paper are printed by scanning of the print head along the face of the sheet. The head structures include three subheads, each having nozzles for printing one or more adjacent lines with the subheads being spaced the same number of lines apart as the number of lines each prints; and three subheads spaced the equivalent of seven lines apart, each subhead having three nozzles spaced at the equivalent of alternate lines. The heads are advanced between scans by an equivalent number of lines generally equal to the number of nozzles in the head, whereby all print lines are addressed only once. Apparatus for printing includes the use of pointers in registers to keep track of head structure and location on a print medium for calculating print addresses. A partial page memory is used which wraps around to the beginning from the end.

Abstract: A logic analyzer has a counter/timer that can reconstruct the higher resolution with which data was acquired using multiple phases of the logic analyzer system clock signal. For a two-phase data sampling system, separate pairs of event recognizers monitor the data collected using the two phases of the system clock. Counter/timer control logic uses the information from these separate pairs of event recognizers to control the behavior of the counter/timer so that it can either single count or double count, depending on whether an event was true during both phases or only one phase of the data acquisition, thus allowing the counter/timer resolution to be as high as the information inherent in the data acquired using both clock phases. The counter/timer employed is capable of single or double counting and has two stages, a prescaler and an extension counter/timer, for increased power and cost effectiveness.

Abstract: A cathode-ray tube (54) includes a bipotential electrode structure (50) that converges the electrons in an electron beam. The bipotential electrode structure includes a cylindrical metallic electrode (56) positioned within a neck portion (66) of an evacuated glass envelope (52) and an electrically resistive coating (58) on an interior surface (60) of the neck portion. The resistive coating has a terminal end (64) positioned adjacent the metallic electrode. An electrically and thermally conductive coating (62) on the interior surface of the neck portion covers the terminal end of the resistive coating and partly overlaps the metallic electrode. The conductive coating functions to prevent electric "punch-through" between the interior and exterior surfaces of the tubular envelope. The conductive coating also allows relatively efficient operation of a beam deflection apparatus.

Abstract: The present invention constitutes a memory system comprising a multiple number of individual memory units (40-47) for storing digital data from a variable number of data input streams and for efficiently using the memory capacities of the memory units in the system by controlling the routing of data between the memory units. Each one of the memory units includes a set of input multiplexers (100-103), a set of shift/shadow registers (110-113) and a memory component (120) having a RAM memory array (121). The components of the memory units are implemented on a single integrated circuit chip. The input multiplexers allow alternate data streams to be selected for input to the shift/shadow registers. The shift/shadow registers are operative for enabling data to be transferred to and from the memory array at speeds slower than the rate at which these data are received by the system.