Abstract: An autocalibrated multistage analog to digital converter precisely maintains appropriate error correction levels for each stage during operation of the converter to minimize quantization errors. An error signal is derived from the digital output of the converter based upon the slope of the input analog signal, determined either explicitly via hardware or implicitly via software, and an overflow/underflow condition. The error signal is fed back to a calibration control circuit to generate individual error correction levels for various variable correction devices within the analog to digital converter, such as a variable analog delay device. The variations from nominal established at calibration that are due to age, temperature or other environmental factors generate the error signal that varies from a nominal value and is fed back to alter the various error correction levels to minimize the error variation.

Abstract: An electrical connector mounting apparatus has an electrically conductive member formed with spring biased fingers, a base portion and a fastening member. The spring biased fingers in conjunction with the base portion provide electrical continuity between the base of the electrical connector and a chassis frame when the connector is inserted into a frame opening. The base portion of the electrically conductive member is captured between the base of the electrical connector and a support member, which prevent excessive connector rotation and provides strain relief between the base portion and the fastening member. The fastening member is spring biased and engages the frame opening during the insertion of the electrical connector into the frame.

Abstract: A single phase, buried channel charge coupled device has a high conductivity layer overlying the pinned regions thereof and extending to the channel stop regions, thereby facilitating the transfer of charge carriers between the channel stop regions and the pinned regions in order that the potential profile underlying said pinned regions may be more readily maintained. Extension of that high conductivity layer over the channel gate electrodes also facilitates the transmission of clocking voltages to the channel gate electrodes and allows the device to operate with decreased power losses.

Abstract: An improved ink cartridge mounting system for a primary ink jet printer including an ink cartridge mounting element having four cartridge receiving openings, each specially configured to receive an ink cartridge containing ink of a particular color. A unique arrangement of six ribs extends from the outer periphery of each cartridge receiving opening to define a distinctive keying pattern adapted to seat an ink cartridge having a fluted end portion configured to mate with the distinctive keying pattern. The unique keying pattern designated for each different color are entirely complementary to a prior keying pattern employed for the same color in an alternate type of ink jet printer but for the provision of at least one additional rib.

Abstract: An integrated circuit probe station comprises a table having a substantially planar upper surface, an IC probe positioned over the table in spaced relationship with the upper surface of the table, a chuck carrier, and a chuck. The chuck carrier has a substantially planar lower surface that is positioned in confronting relationship with the upper surface of the table, and a film of viscous material is interposed between the upper surface of the table and the lower surface of the chuck carrier, whereby the chuck carrier may be moved manually relative to the table in horizontal directions while resting on the table. The chuck is carried on the chuck carrier and is movable vertically relative to the chuck carrier. A mechanical prime mover is effective between the chuck carrier and the chuck for bringing about vertical movement of the chuck relative to the chuck carrier.

Abstract: A synchronous programmable binary counter has a parallel section and a serial section, with the length (in bits) of the serial section being the same as the modulus of the parallel section. The parallel section counts on system clocks and produces two outputs. A parallel terminal count output is produced each time the parallel section count reaches a programmed value. A frame output is generated every time the parallel section reaches its maximum count and starts counting again. The serial counter section decrements its programmed value by one each time it receives a frame signal from the parallel section. This subtraction is accomplished by a half-adder and associated borrow flip-flop. The borrow flip-flop is set by each arrival of the frame signal. Between frame signals, the decremented programmed value is circulated in a shift register as the serial subtraction process is performed.

Abstract: A microprocessor controlled test system generates and transmits distorted digital signals to a system under test by expanding a bit pattern, representative of a character to be transmitted, by an integer multiple of expansion. Selected bits of the expanded bit pattern are toggled from one logic level to another under program control to produce a distorted expanded bit pattern. The distorted expanded bit pattern is clocked out of the test system to the system under test at a rate equal to the integer multiple of expansion times the baud rate of the system under test. The resolution of the test signal can be varied by changing the integer multiple of expansion along with the rate at which the test signal is clocked out of the test system. The invention is useful in testing and adjusting a teletypewriter.

Abstract: A circuit board configuration for I/O devices and logic devices, wherein the I/O devices have current levels substantially higher than the current levels associated with the logic devices. The I/O devices are grouped adjacent a connector, and a ground return plane surrounds the I/O devices coupling the ground terminals of the I/O devices to the ground pins of the connector. The logic devices are spaced some distance away from the connector where the ground terminals of the logic devices are connected through vias to a ground plane. The ground return plane, forming a strip line with the ground, plane, is effective for isolating the I/O devices and reducing signal distortion on the board.

Abstract: A mixed bipolar-CMOS self-aligned process and integrated circuit provide a high performance NPN bipolar transistor in parallel to fabrication of a PMOSFET and an NMOSFET. Gate and base contacts are formed in a first polysilicon layer. The base contacts are implanted with P+ ion concentrations for diffusing base contact regions of the substrate in a later drive-in step. Source and drain contacts and emitter contacts are formed in a second polysilicon layer. The source and drain contacts are formed as a unit and then separated into discrete contacts by a spin-on polymer planarization and etch-back procedure. Lightly-doped lateral margins of the source, drain and base regions are ion-implanted in an initial low concentration (e.g. about 10.sup.13 atoms/cm.sup.2). The gate and base contact structures serve as a mask to self-align the implants. Then, the gate and base structures are enclosed in an oxide box having sidewalls.

Abstract: A multiphase memory array is read out using two multiplexers and a demultiplexer under the control of a state machine. The state machine enables one portion of the memory array at a time using a gate to multiplex the memory portion outputs. While a particular portion is enabled, a bit multiplexer associated with that portion is directed by the controlling state machine to sequentially select each bit at the current address in that memory portion for output. A shift register demultiplexer performs serial to parallel conversion on the sequential bits from each memory portion to convert them to a readback byte or word for output. After the byte or word has been read out, the state machine enables the next portion of the memory array and repeats the multiplexing and demultiplexing process for the data at the same address in that memory portion. When all of the memory portions have read out, the address to the memory array is changed and the whole process is repeated for the data at the new address.

Abstract: A liquid crystal cell (10) includes a chiral liquid crystal material (16) captured between a pair of electrode structures (12 and 14). The liquid crystal material is of a type that exhibits in consecutive order chiral semitic nematic, smectic A, and chiral phases at successively lower temperatures. In a preferred embodiment, the chiral phase is of the smectic C type. The electrode structures have director alignment layers (22 and 22') deposited on their inner surfaces. The directors (28 and 30) of the liquid crystal material in the nematic phase in contact the alignment layers align at relatively large tilt bias angles relative to the alignment layer. The tilt bias angles of the directors in contact with one of the electrode structures are defined in a rotational sense which is opposite that of the tilt bias angles of the directors in contact with the other electrode structure.

Abstract: Apparatus for correcting astigmatism produced by the electromagnetic deflection yoke of a cathode-ray-tube includes stigmator electrodes provided with elongated slots through which the cathode-ray-tube's electron beam or beams pass. Appropriate correction voltages, stored in digital memory, are applied to the stigmator and focus electrodes for bringing about re-focusing of the electron beam in appropriate axes for restoring a single point focus.

Abstract: A serial dynamic memory shift register is configured in the form of an array of dynamic memory cells. Each dynamic memory cell is coupled to a column data bus and is addressed by an individual row command, and the data from the dynamic memory cells are transferred serially from the cells via a temporary latch. The dynamic memory cells and the temporary latch form a subarray, and a plurality of subarrays connected in series form a one-bit slice. A plurality of one-bit slices connected in parallel to receive the multiple bits of a data word in parallel forms a one-word slice. Each one-word slice has an data input latch to transfer data from an input data bus to the one-word slice, and an data output latch to transfer data from the one-word slice to an output data bus.

Abstract: An addressing structure uses an ionizable gas to address data storage elements (16) defined by the overlapping areas of multiple column electrodes (18) on a first substrate (48) and multiple channels (20) on a second substrate (54). A layer of dielectric material (46) separates the first and second substrates. Each of the channels is filled with the ionizable gas and includes a reference potential electrode that receives a data drive signal and a row electrode that receives a data strobe signal. For each storage element, the ionizable gas functions as an electrical switch that changes between a conducting or plasma state and a nonconducting or de-ionized state in response to an applied data strobe signal. The ionizable gas functions to either store data in or read data out of the storage element.

Abstract: Jitter in a clock signal is measured by using the clock signal to clock a digitizer repetitively digitizing a highly stable sine wave signal so as to produce a first data sequence representing the magnitiude of the sine wave signal as a function of time. This first data sequence is normalized to produce a second data sequence having data elements that vary between maximum and minimun magnitudes of +1 and -1. The arcsine of each element of the second data sequence is then determined to provide a monotonically increasing third data sequence, wherein each element of the third data sequence indicates a phase angle associated with a corresponding element of the second data sequence. A fourth data sequence is then generated, each element of the fourth data sequence representing a difference between a phase angle represented by a corresponding element of the third data sequence and a phase angle that the corresponding element of the third data sequence would represent if the clock signal had a constant frequency.

Abstract: A fluid pressure regulator comprises a housing defining a cylindrical chamber, an inlet opening for introducing fluid under pressure into the chamber, an outlet opening for allowing fluid to leave the chamber at a regulated pressure, and a bleed orifice in communication with a space at constant pressure. The outlet opening and the inlet opening are in open communication. A ferromagnetic piston member is fitted in the chamber and is slidable within a range of positions such that the bleed orifice is partially covered by the piston. The ferromagnetic piston member is biased at a substantially constant force when it is that range of positions.

Abstract: An integrated circuit formed in a semiconductor die which has at least two distinct functional regions is treated by mounting the die by way of its front face on a support member, and subsequently removing die material by way of its back face so as to physically separate the functional regions of the die from each other.

Abstract: An electrical test probe has a electrically conductive hollow elongate body with an exterior coating of electrically insulative material. An output connector is formed by soldering an electrically conductive wire to the exterior of the elongate body. A hooked gripping tip for probing Integrated circuit devices and the like is formed on one end of a conductive shaft inserted into the elongate body. Axial movement of the conductive shaft relative to the elongate body alternately extends and retracts the hooked gripping tip out of and into the elongate body. The electrically conductive elongate body provides a low contact resistance path between the gripping tip and the output connector.

Abstract: A charge-coupled device comprises a body of semiconductor material having a channel along which charge can be transferred in a predetermined transfer direction by charge carriers of a first polarity, and a plurality of gates over the channel, the gates being in n sets, where n is an integer greater than unity. The gates of the jth set, where j is in the range of 1 to n, are longer in the transfer direction than the gates of the kth set, which precede the gates of the jth set. The kth set of gates are driven between first and second potential levels of which the first potential level is of the first polarity relative to said second potential level, and the jth set of gates are driven between third and fourth potential levels of which the third potential level is of the first polarity relative to the fourth potential level and is of a second polarity relative to the first potential level.

Abstract: A probe assembly for use in testing an integrated circuit embodied in an integrated circuit chip in wafer form, comprises a stiff support member formed with an aperture, and a membrane. Both the support member and the membrane comprise dielectric material and portions of conductive material supported by the dielectric material in electrically-insulated relationship. The portions of conductive material of the membrane constitute inner contact elements distributed over a main face of the membrane in a pattern that corresponds to the pattern in which contact areas are distributed over the contact face of the chip under test, outer contact elements distributed about a peripheral region of the membrane in a second pattern, and transmission lines extending from the inner contact elements to the outer contact elements respectively.