Abstract: A hand-held inertial mouse provides input data to a computer from which the computer can determine the translational and angular displacement of the mouse. The mouse includes accelerometers for producing output signals of magnitudes proportional to the translational acceleration of the mouse in three non-parallel directions. Pairs of these accelerometers are positioned to detect acceleration along each axis of a cartesian coordinate system such that an angular acceleration of the mouse about any axis of rotation causes representative differences in the magnitudes of the output signals of one or more of these accelerometer pairs. The translational velocity and displacement of the mouse is determined by integrating the accelerometer output signals and the angular velocity and displacement of the mouse is determined by integrating the difference between the output signals of the accelerometer pairs.

Abstract: A current source provides an output current whose magnitude is substantially independent of changes in temperature. In each of three embodiments (50, 100, 120), one or more bipolar transistors are employed to provide a compensating current which is dependent on the base-to-emitter voltages, V.sub.BE, of such bipolar transistors. The compensating current changes with temperature so as to offset changes in the uncompensated output current so that the total output current is substantially independent of V.sub.BE. The three embodiments employ current mirror circuits (10, 122) that provide a current source of simple circuit design that is operable with the use of a single power supply at a relatively low voltage.

Abstract: A logarithmic amplifier calibrator internal to an electronic instrument applies a swept frequency signal via a switch and a single pole resonator to a logarithmic amplifier to be calibrated. The logarithmic amplifier output is digitized and stored as a frequency response for the resonator. The switch is opened and the single pole resonator rings down through the logarithmic amplifier. The ringdown output of the logarithmic amplifier also is digitized and stored as a linear log response. A ripple error look-up table is generated from the linear log response. An approximate bandwidth for the resonator is determined from the frequency response and a ringdown time corresponding to the time the linear log response decreases from the maximum amplitude to a 3 dB down amplitude of the frequency response to determine the exact bandwidth for the resonator.

Abstract: A liquid crystal cell (40) for an electron beam-addressed liquid crystal light valve has a rigid glass substrate (16) and target substrate (44) formed of thin flexible material. The cell (40) is constructed so that the spacing between the flexible substrate (44) and the rigid substrate (16) is precisely maintained. A fixture (72) is employed for attaching the target substrate (44) to the rim (102) of the light valve body (14) prior to assembly of the cell (40).

Abstract: An active electrical test probe with wideband frequency capability for use on a test probe card, along with other test probes. A small hybrid integrated circuit is mounted on a substrate held on edge, adjacent the probe tip contact element of the probe, by a conductive metal clip. The circuit is provided power from an external source. Signals received by the probe tip are transmitted, as modified by the hybrid integrated circuit, through an output cable to electronic test equipment.

Abstract: A degaussing system for a CRT includes a voltage source, which is enabled by power-up of the CRT, coupled to a tank circuit including a degaussing coil and a capacitor. A voltage sensing network connected in parallel with the tank circuit senses the voltage across the capacitor and when that voltage rises to a predetermined threshold, and actuating signal is provided which turns on a latching switch circuit which enables a switch connecting the tank circuit to ground. This allows it to oscillate, taking the metal components of the CRT through a decreasing series of hysteresis loops as the oscillation decays. The latching switch circuit maintains the switch in an on position until power-down of the CRT, thus maintaining all except R1 which aids grid regulation of the components of the degaussing system, in a low voltage state until degaussing becomes necessary once again.

Abstract: An electronic device measurement apparatus measures a characteristic of an electronic device under test (DUT) by applying a sine-wave voltage to the DUT, detecting the voltage across the DUT as well as the current flowing through the DUT and displaying a characteristic curve in accordance with the detected voltage and current. The sine-wave voltage is generated in phase with an AC line voltage but the amplitude thereof is independent of the line voltage, and consequently the circuits in the measurement apparatus are not affected by variations in phase and amplitude in the line. Moreover, the generated sine-wave voltage is symmetrical, whereby display distortion is substantially eliminated. A voltage limiter and a current limiter are provided for limiting the voltage and current to be applied to the DUT to values determined by a display window, for protecting a current detecting resistor and a voltage divider connected to the DUT.

Abstract: A variable resolution system for a potentiometer converts the analog output of the potentiometer to digital steps which are multiplied to provide a number of digital output steps dependent upon the extent of potentiometer movement since last reversal. Upon each reversal, the number of output steps per input step is reduced to provide greater resolution.

Abstract: A color graphic display system has self-test capability for testing system elements between the frame buffer and the display monitor inputs. The DAC output analog signals are converted to a digital signal and processed to provide an output test bit, which is input to the graphics processor. Additional self-test hardware includes address and data lines from the graphics processor to the color map for directly loading test bit patterns into the color map. The system self-tests the frame buffer, shift registers and DACs by loading various predetermined test bit patterns into the frame buffer and the color map; cycling that data through the display system; reading the test bit; comparing the output test bit values to expected values; and reporting any errors detected. The system also includes a method for self-testing the refresh counter address path into the frame buffer.

Abstract: An edge connector for connecting a conductor run on an edge region of a first circuit board to a conductor run of a second circuit board comprises a plate of dielectric material. The plate has a generally U-shaped portion, with the two limbs of the U defining a slot therebetween. The plate of dielectric material may be attached to the second circuit board in a position such that an edge region of the first circuit board may be received in the slot. A signal conductor is adhered to one main face of the plate of dielectric material and has two end portions. One end portion of the signal conductor projects from one of the limbs of the U into the slot for engaging a conductor run on the edge region of the first board, and the other end portion projects from the plate at a location remote from the slot for contacting a conductor run of the second board.

Abstract: A bus arbitration controller controls access of a plurality of asynchronous potential master devices to a unitary interconnecting bus by forming a distributed state machine of arbitration logic units in each of the potential master devices. Each arbitration logic unit receives control signals by way of the unitary bus which are common to all the devices, each control signal being the logical OR of the corresponding signals from all other devices. The control signals include a device address/priority number and a synchronization signal set. The arbitration logic includes a priority resolver which awards bus access to a device having the highest address/priority number, and control logic which receives the common synchronization signal set and synchronizes the operation of the device in which the arbitration logic resides with all other devices contending for the unitary bus. The control logic and the priority resolver are programmable array logic circuits.

Abstract: A digital storage oscilloscope comprises an analog-to-digital converter for receiving an analog input signal and generating a succession of data words representative of the instantaneous magnitude of the input signal at a succession of equally-spaced sample times. A waveform memory has a plurality of separately addressable storage locations for storing the succession of data words at locations of which the addresses are related to the respective sample times. A trigger circuit compares the instantaneous magnitude of the analog input signal with a predetermined trigger level and generates a trigger pulse when the instantaneous magnitude of the input signal bears a predetermined relationship to the trigger level. The trigger circuit also causes an address word to be stored that defines the storage location for the first data word that occurs after the trigger pulse.

Abstract: A method of measuring automatically the peak-to-peak amplitude of electrical input signal utilizes both trigger circuits of a dual trigger oscilloscope. The steps of the method include adjusting automatically the trigger level of the first trigger circuit until the first trigger level is equal to the maximum peak of the input signal while adjusting automatically the trigger level of the second trigger circuit until that level is equal to the minimum peak of the signal. The second level is then subtracted from the first level to calculate the amplitude. To minimize the time involved, the method distinguishes between signals faster than and slower than a preselected frequency and calculates more rapidly the amplitude for faster signals. Time is also minimized by adjusting hysteresis levels and voltage level settling times as the trigger levels are increased and decreased in search of the peak signal values.

Abstract: An improved cascomp amplifier includes a main differential transconductance amplifier stage, a pair of diode connected sense transistors and a differential correction amplifier stage. The sense transistors present a precise measure of the error voltage to the correction amplifier and extend the reverse breakdown voltage of the input stage of the main amplifier. The sense transistors are also used to correct additional gain variations due to transistor beta. The correction amplifier provides a current which cancels the nonlinearities of the main amplifier. The configuration of the correction amplifier reduces the capacitive load to the main amplifier thereby reducing aberrations in the transient response.

Abstract: A fast latching flip-flop has a transparent latch master section with an input amplifier, an output latch, a current source connected to provide current for the input amplifier and the output latch, and a switch for applying the current from the current source to either the input amplifier or the output latch. A slave section is connected to the output latch to transfer the data from the output latch to the output of the fast latching flip-flop. A delay transistor is inserted between the switch and the input amplifier to add delay in the turn-off of the input amplifier. Additional delay is attained by connecting a plurality of diode-connected transistors to the junction of the delay transistor and the switch. The result is a reduction of the metastable region between the turn-off of the input amplifier and the turn-on of the output latch.

Abstract: A heterodyne color signal recognition circuit generates an error signal for each horizontal line of an input video signal for which the phase relationship of the horizontal sync pulse and color subcarrier burst exceeds a given phase relationship by a predetermined tolerance. The error signals are summed over a video field to produce a preliminary non-direct color signal for the video field. Preliminary non-direct color signals for successive video fields are digitally filtered to generate a non-direct color signal indicative of a heterodyne color signal source, the non-direct color signal being used to automatically switch in a time base corrector between the input video signal and further video processing.

Abstract: An automatic picture coding system including a method for converting a bit-map image of the picture to vectors as the picture is being scanned. The bit map is delayed as it is being generated to form a series of tessellations or windows of data. The windows are propagated through a series of neighborhood-logic elements which perform data transformation operations such as growing, smoothing and thinning of the bit-map image. A bit stream output from the neighborhood logic which output includes only line and edge features of the original picture is transferred serially to a microcomputer where the features are partitioned into a plurality of line segments. Each line segment is chain coded and temporarily stored, as it is acquired, in a corresponding one of a plurality of lists, the lists being linked in an order corresponding with the order in which the segments are acquired.

Abstract: An optical phase shifter comprises an optical waveguide of electro-optic material and an electrode structure associated with the waveguide for imposing an electrical field on the waveguide. The electrode structure comprises at least two groups of electrodes, each group having at least first and second electrodes between which the waveguide passes. The first electrode of one group and the second electrode of the other group are on opposite respective sides of the waveguide and are connected to respective input terminals for receiving an electrical signal. The second electrode of the one group is connected to the first electrode of the other group.

Abstract: A method and apparatus for measuring the width of pulses in the gigahertz range comprises the steps of splitting an input pulse and delaying one of the pulses prior to their recombination in a directional coupler. The recombined pulse is then measured in a power meter. By varying the delay, maximum and minimum readings from the power meter may be found. The pulse width may then be found as a function of the actual delay, which may be controlled by the user by varying the distance through a waveguide that the delayed pulse must travel.

Abstract: Information for a histogram is provided through generation of a pseudo-random sequence in a shift register connected in predetermined feedback relation. A histogram element storage location is addressed in a random access memory and is used for loading the shift register in parallel when an event corresponding to that element takes place. The shift register proceeds from that point to increment a pseudo-random sequence for the duration of the event, and the concluding value of the sequence is loaded back into the random access memory location at the conclusion of the event. A network between the random access memory and the shift register loads the shift register with a pattern that replicates the pattern that would exist in the shift register if the shift register had already been loaded and the data therein was shifted once.