Abstract: A multiple port memory includes a set of memory units each comprising a set of memory cells, one corresponding to each port. Each cell of a memory unit stores a single data bit and each cell is independently read and write accessed through separate data, address and control busses. The cells of each memory unit are cross-coupled so that when the state of the bit stored by one of the cells of a memory unit is changed when write accessed, the other cells of the memory unit thereafter change the states of their stored bits in the same way.

Abstract: A bipolar-CMOS (Bi-CMOS) digital interface circuit (50) of the present invention provides an interface between a bipolar digital circuit (52) and a CMOS digital circuit (54). The digital interface circuit includes a digital transform circuit (56) that receives a bipolar logic signal generated by the bipolar digital circuit and transforms the signal into an intermediate logic signal whose voltage waveform is positioned symmetrically about a logic threshold generated by a CMOS digital input circuit (58). The CMOS digital input circuit receives the intermediate logic signal and generates a CMOS logic signal that is delivered to the CMOS digital circuit, thereby to interface the CMOS digital circuit with the bipolar digital circuit.

Abstract: A clock signal is transmitted to nodes of each of several interconnected circuits through a separate adjustable delay circuit, the time delay of each delay circuit being adjusted so that the clock signal arrives at each node at the same time, thereby synchronizing operation of the separate integrated circuits one to another. Each delay circuit comprises a set of signal delay elements which can be selectively switched into the clock signal path so that the clock signal delay may be adjusted by adjusting the number of signal delay elements in the clock signal path. Each signal delay element itself has a unit delay adjustable in proportion to an applied control voltage generated by a delay element monitor. The delay element monitor measures the unit delay in relation to the period of a stable reference clock and adjusts the delay of each delay element as necessary to ensure that the unit delay remains constant.

Abstract: An integrated pad switch has conductive contacts that may be embedded in a flexible substrate to form a wiper contact. The flexible substrate is backed by a foamed elastic block and mounted on a driver. The wiper contact moves across the surface of a hybrid circuit substrate having an electrical circuit to provide the desired switching function.

Abstract: The relative gain and/or delay of two signal transmission channels may be measured by impressing on each channel a repetitive signal comprising a burst packet. The burst packets of the signals applied to the channels are of constant, but different, frequencies, and their amplitudes are related in predetermined manner. The two burst packets are timed to have a predetermined phase relationship at a selected time during the packets. The output signals of the two channels are additively combined, and a determination is made as to at least one of (a) the amplitude of the combined signal at a turning point in the amplitude of the signal envelope and (b) the time relative to the selected time at which a turning point in the amplitude of the signal envelope occurs.

Abstract: A ferrimagnetic resonator has improved high frequency response because a shorter, tapered pole shaft is substituted for the longer pole shafts of uniform dimensions in the prior art. This shorter, tapered shaft alleviates constrictions in the field of the magnetic flux, thus allowing for an improved flux density at the tip of the magnet and correspondingly improved high frequency operation of the ferrimagnetic resonator. In a preferred embodiment, the tip of the pole is replaced with a layer of a higher permeability, but also higher hysteresis, alloy to improve the flux density in the air gap where the ferrimagnetic crystal resonator elements reside. In alternative embodiments, the case end of the pole shaft can attain its greater dimensions because of sides that curve outward or that get larger in a series of steps.

Abstract: A graphics display system (10) includes a display screen (14) on which images are formed and a data transform circuit (12) that provides transformations between model data representing the basic shape of an object and display data that are employed in the formation of an image of the object on the display screen. The model data are transformed into display data in accordance with position data and orientation data that correspond, respectively, to a translation and a rotation of the image on the display screen. The data transform circuit communicates with a central processing unit (30) that controls the operation of the graphics display system. The data transform circuit includes data storage registers (34, 36, 38, 40, 42, 44, 46) that receive and hold the model, position, and orientation data. A multiplier circuit (68) and an adder circuit (112) calculate the transformation of the model data into display data.

Abstract: An intermediate structure in the fabrication of a metal-oxide semiconductor field-effect transistor is made from a substrate of p+ silicon having an elongate insulated gate structure on its main face. First and second areas of the main face are exposed along first and second opposite sides respectively of the gate structure. Donor impurity atoms are introduced into the substrate by way of at least the first area of the main face, to achieve a predetermined concentration of electrons in a region of the substrate that is subjacent the first area of the main face. The gate structure is opague to the impurity atoms. A sidewall of silicon dioxide is formed along the first side of the gate structure, whereby a strip of the first area of the main face is covered by the sidewall and other parts of the first area remain exposed adjacent the sidewall.

Abstract: A step transition time reduction technique for a YIG oscillator having a capacitive filter uses an inverse transfer function to produce a predistorted drive step signal from an input drive step signal, the predistorted drive step signal being used to drive the YIG oscillator. The inverse transfer function uses R,L,C values from the oscillator circuit to generate an intermediate step in the input drive step signal, the value of the step being determined by a factor k=1/(1+e.sup.-a*pi/b) and the duration of the step being determined by a delay time dt=pi/b, where a=R/(2L) and b=(1/(LC)-R.sup.2 /(4L.sup.2)).sup.1/2.

Abstract: According to the present invention, an R-S latch includes an input stage, a double gate latch stage, and an output stage. The input stage includes a pair of source couplet FETs, a pair of active loads, and a biasing current source. The output of the input stage is coupled to both the latch stage and the output stage, which contains a pair of source follower FETs. The latch stage includes a pair of source coupled double gate FETs. The latch stage provides the switching or latching mechanism which prevents the outputs from changing logic stage until an appropriate set or reset pulse is received. However, one pair of the gates in the latch stage are coupled to an inverted set and reset input. This pair of additional gates enables the Q and Q output to switch symmetrically, thus preventing delay between the Q and Q output.

Abstract: A knock-out in the wall of the housing for electronic equipment is selectively removed to provide a knock-out opening. A wall includes first and second slits positioned along the boundary of the knock-out and separated by a land. The wall includes a break out opening adjacent to each land. Break portions of the wall separate the break out opening from the first and second slits. These break portions are severed to interconnect the first and second slits through the break out opening and permit removal of the knock-out. Plural such slits and break out openings are provided and arranged to provide a knock out of rectangular or other desired geometric shape. The slits and break out openings are sized to provide electromagnetic interference shielding. Also, the break portions are of a length which is approximately no greater than the thickness of the wall and are positioned to facilitate removal of the knock-out without deforming the wall and without leaving burrs in the knock-out opening.

Abstract: Stored waveform records representative of respective repetitions of a repetitive signal are processed by reading a first waveform record from memory to form a reference signal. A second waveform record is read from memory to form a second signal, and the second signal is shifted in time in such a manner as to minimize the power of a difference signal, of which the instantaneous magnitude is representative of the difference in instantaneous magnitude between the reference signal and the time-shifted second signal. If the waveform records are identical but for jitter, and the power of the difference signal is brought to zero, this implies that the first waveform signal is synchronous with the processed second waveform signal, i.e., there is no jitter between the two signals.

Abstract: An interface circuit in a modular electronic system includes duplex control-signal transmission lines. Modules connectable to a controller unit of the system transmit configuration data items by way of the duplex lines to the controller during a first time period, and the controller during a second time period generates module control signals in accordance with the configuration of the modules. The module control signals are transmitted to the modules on the duplex transmission lines.

Abstract: A multilevel logic circuit includes a pair of resistors coupling collectors of an emitter-coupled pair of transistors to a voltage source, and includes a switch selectively connecting the emitters of the transistors to a current source. When the switch is closed, an input signal applied across the bases of the transistors controls an output signal produced between their collectors. When the switch is open, both transistors are off and the output signal is not affected by the input signal. A clamping circuit connected to a circuit node at the emitters of the transistors maintains a constant voltage at the node sufficient to prevent leakage current from charging or discharging inherent circuit capacitance at the node when the switch is open.

Abstract: A digital signal synthesizer stores a representation of a desired analog signal in the form of digital samples. The digital samples are converted to an analog signal by a sample clock having a frequency greater than or equal to twice the bandwidth of the desired analog signal. The analog signal is band pass filtered to recover the desired analog signal.

Abstract: A digital-to-analog converter filter circuit includes a means for generating a blanking signal to coincide with a change in the digital signal value to the converter and an analog switch controlled by the blanking signal. The analog switch receives the analog signal from the converter and passes the signal depending on the state of the blanking signal. The blanking signal controls the switch to block passage of the analog signal for a predetermined time sufficient for the analog signal to settle after transition from a first value to a second value in response to the change in the digital input signal value. The analog switch is connected to a vector filter which receives the analog signal and transmits a delayed transition signal from the first analog signal value signal to the second value. The filter transmits the first value until the switch passes the second value upon command of the blanking signal.

Abstract: A trigger circuit for detecting plural simultaneous input signals and generating a trigger signal in response thereto includes a word recognizer and a state machine. The word recognizer reconstructs eacg input signal in response to predetermined high and low threshold voltage logic levels and the input signal. The reconstructed signals indicate the input signal's logic level above the high threshold level, below the low threshold level, and transitionally between the high and low logic levels. The trigger circuit provides both clock-based and time-based trigger modes. The clock-based trigger modes include single event triggering, nested event triggering, and consecutive and exception event triggering. The time-based trigger modes include these modes and in addition setup and hold-time triggering, transition time triggering, and sliver pulse triggering.

Abstract: Menus displayed on a screen of an instrument permit an operator to adjust and monitor the operating state of the instrument. Various menus are added and removed from the display in response to changes in the operating state of the instrument so that those menus appropriate for the operating state of the instrument are automatically displayed while inappropriate menus are automatically removed from the display. Displayed menu items may be added, removed or modified in response to changes in the operating state of the instrument, as evidenced by changes in the configuration parameters, so that only those menu items which are appropriate to a given operating state are displayed.

Abstract: A circuit produces an output binary floating point number approximating with high accuracy the inverse of an input binary floating point number D in accordance with the expression (1/D).apprxeq.[(1/A)-C]+[C-(B/A.sup.2)], where the number A is a low accuracy approximation of D, and B is substantially equal to D-A. C is a number selected for each value of A such that the exponents of quantities [(1/A)-C] and [C-(B/A.sup.2)] are equal to the exponent of the quantity 1/2A. Quantities [(1/A)-C] and [C-(B/A.sup.2)] are produced by lookup tables and summed to provide an approximation of 1/D.

Abstract: A record in which a color is represented on a record medium at a selected gray scale level is created by resolving an addressable area of the record medium into a square array of addressable record locations and organizing the record locations into a plurality of groups each containing a 4.times.4 array of record locations. The groups are organized into a plurality of dither cells each containing a 4.times.4 array of groups, whereby each dither cell contains 256 addressable record locations. An [i+(j.times.16)]th gray scale level is established within a selected area of the record medium, where i is an integer in the range from zero to 16, j is an integer in the range from zero to 16 and [i+(j.times.