Abstract: A logic analyzer for measuring individually a plurality of logic signals transmitted via a multiplexed digital bus in a time-sharing manner is disclosed. First and second memory circuits store respectively first and second logic signals of the multiplexed digital bus in accordance with first and second strobe signals synchronized with the first and second logic signals.

Abstract: An improved lateral convergence deflection system for a delta-gun shadow mask color CRT includes first, second and third lateral convergence coils mounted on the CRT neck radially outward from the paths of the electron beams from the three guns. The coils are connected in series electrically, and are of suitable strength and orientation to provide a substantially unidirectional, vertical field in the path of one (e.g., the blue) beam, and field nulls in the paths of the other two (e.g. the red and green beams). By varying the current passed through the coil by a convergence drive amplifier, the blue beam may be shifted laterally without producing any substantial movement of the other two beams.

Abstract: A circuit including a conventional digital-to-analog converter (DAC) and a charge pump for producing an analog representation of an input waveform defined by an input digital bit stream, the analog representation being relatively free of spurious aberrations usually present in the output of a conventional DAC. The charge pump and an associated integrator are used to produce a first approximation of the input waveform and the DAC and an associated detuned slew-rate filter are used to maintain the first approximation in long-term conformance with a more accurate second approximation. Spurious aberrations in the second approximation are integrated over several steps of the input bit stream, thereby minimizing their adverse impact on the relatively true first approximation.

Abstract: A logic analyzer which can simultaneously measure one block of input data in detail and the same or another block of input data in rough form is disclosed. The logic analyzer comprises first and second sections each including a memory circuit to store the input data and a word recognizer to detect the desired trigger word from the input data. These first and second sections receive different clocks having different rates, and the second memory circuit stores the first clock applied to said first section for recognizing the time relationship of these clock signals. A counter counts the first clock in accordance with the outputs from the first and second word recognizers for recognizing the time relationship of the first and second trigger words.

Abstract: A gating circuit for a universal counter comprises a pair of flip-flops and a pair of logic gates arranged to provide any of a plurality of counting or timing measurements. A gate control circuit includes a control logic unit to provide routing and synchronization of digital signals from several inputs, including an internal source as well as a pair of external sources, into one or both of a pair of count chains.

Abstract: Thin film multilayer technology is used to build microminiature electromechanical switches having low resistance metal-to-metal contacts and distinct on-off characteristics. The switches, which are electrothermally actuated, are fabricated on conventional hybrid circuit substrates using processes compatible with those employed to produce thin-film electrical circuits. In a preferred form, such a switch includes a cantilever actuating member comprising a resiliently bendable strip of a hard insulating material (e.g., silicon nitride) to which a metal (e.g., nickel) heating element is bonded. The free end of the cantilever member carries a metal contact, which is moved into (or out of) engagement with an underlying fixed contact by controlled bending of the member via electrical current applied to the heating element.

Abstract: An apparatus of providing vertical smoothing of convergence correction signals in a digital convergence system is disclosed. The surface of a cathode ray tube is subdivided into a matrix including a plurality of intersecting rows and columns and having a plurality of intersections corresponding thereto. A value is assigned to each intersection of a row and a column of said matrix. An electron beam traces a plurality of scan lines within each of the rows of the matrix. For each scan line within a row of the matrix, a convergence correction signal is synthesized using the plurality of values associated with the plurality of intersections in said row. A plurality of horizontal discontinuities are present in the convergence correction signal as a result of the different magnitudes associated with the plurality of values used to synthesize the convergence correction signal.

Abstract: A non-linear amplifier circuit that may be used to provide a logarithmic amplification characteristic. The circuit includes an amplification stage employing positive non-linear feedback for low level input signals to reduce the input capacitance of the amplifier. For large level input signals the feedback is eliminated.

Abstract: An improved calibration reference signal generator that includes both preset and variable means for generating digital signals corresponding to reference voltage levels. The digital signals are coupled through a chopper switch to a first DAC, which produces a square wave analog signal having an amplitude equal to the desired reference voltage. The digital signals also are coupled directly to a second DAC, which converts at least the most significant bit of the signals to a corresponding offset voltage. An output amplifier combines the square wave signal and offset voltage to produce an output square wave signal with a d.c. offset proportional to the amplitude of the square wave signal. In an alternative mode of operation, the output of the second DAC is disconnected from the output amplifier, which then produces a square wave signal without any offset.

Abstract: A programmable pulse generator which generates a pulse having programmable leading and trailing edges is disclosed. An oscillator starts to generate a pulse in response to a trigger signal, and the pulse is counted by a counter for generating an address signal. A memory circuit generates a pulse having predetermined time occurrence of leading and trailing edges in accordance with the address signal, and the transition detector detects the trailing edge to stop the oscillation of the oscillator.

Abstract: An apparatus and method for expanding the resolution of digital-to-analog converters is described. Two limited resolution digital-to-analog converters are cascaded in such a manner that one converts the low order bits of digital input signal and the other converts the higher order bits. The output of the higher order digital-to-analog converter is applied directly to a summing circuit while the output of the low order digital-to-analog is first passed through an attenuator. When the low order digital-to-analog converter receives all logical ones, a carry is performed to the higher order digital-to-analog converter. The low order analog-to-digital converter is then reset by a successive approximation technique. Operation is essentially the same for borrow operation.

Abstract: An active voltage probe receiving a DC power voltage via an outer conductor of a coaxial cable is disclosed. The probe includes a differential amplifier with inputs connected to input and reference terminals via DC paths and a follower amplifier with an input connected to the input terminal via an AC path. Outputs currents from the differential and follower amplifiers are applied to an inner conductor of the coaxial cable.

Abstract: A multiburst test signal generator and a method for using the generator's test signal to determine the frequency response characteristics of television video circuits with a high degree of accuracy is described. One of the burst frequencies is continuously enabled and made variable and the other burst frequencies are disabled. The resulting continuous sine wave is applied to the circuit being tested, its frequency is varied, and the output of the circuit being tested is monitored with a conventional frequency counter.

Abstract: A memory patching system which transfers permanent-type information in a read-only memory (ROM) to a random access memory (RAM) and modifying contents of the RAM in accordance with patch information in an eraseable programmable ROM is disclosed.

Abstract: This invention is designed to protect a resonant scan deflection transistor in a deflection circuit from extremely high flyback voltage pulses. The deflection transistor is protected against high flyback voltage pulses even though: the B+ voltage on the deflection circuit varies over a wide range, the rate of the base drive signal varies over a wide range, and the turn-off delay time of the deflection transistor varies from device to device and for any one device as the base drive signal rate changes. The circuit of this invention compensates for the variations in turn-off delay time (t.sub.D) of the deflection transistor at different horizontal scanning rates, and, in response to this compensation, compares the B+ voltage level with the current in the deflection coil. An extra turn-off trigger signal is developed in response thereto for energizing the deflection transistor drive circuit. In response to the trigger signal, the deflection transistor turns off.

Abstract: This disclosure describes an electrical connector for joining microcircuit or microcircuit modules, such as leadless integrated or hybrid circuit carriers to utilization means, such as printed or etched circuit boards or similar means. The electrical contacts through which the microcircuit and utilization means are connected are formed and etched in place on an elastomeric material, precisely located; the material acting as a restoring force to maintain connection. The connector when used in a system maintains transmission line mediums in a single environment.

Abstract: A circuit for enhancing the performance of a random-access-memory-based memory expansion system is disclosed. Memory capacity and a control register are added to the traditional memory mapping circuit. The increased memory is utilized to store several maps simultaneously and the circuit output is then switched from one stored map to another according to data present at the control register outputs. Thus, by pre-loading the circuit with all the memory maps required by a particular program, delay caused by map changes is reduced to the time required to move data to the control register outputs.

Abstract: A one-piece molded plastic quarter-turn fastener is provided for releasably latching a panel to a cabinet. A generally disc-like body has a flanged and slotted stem axially extending therefrom to be snapped into a hole in the panel. Projecting radially from the body is a latching lip for engaging and disengaging a cabinet. A positioning boss is provided to permit a quarter-turn rotation of the fastener with a detent provided at each rotational limit.

Abstract: A buffer amplifier suitable for use as an input amplifier for an oscilloscope comprises a hybrid FET-bipolar transistor source follower input stage and a complementary emitter follower output stage. Both the input and output stages include bootstraps to eliminate thermal transient response aberrations, to increase input impedance, and to maintain standing current in the output stage. Other attributes include a very short response time for high bandwidth operation, and high linearity.

Abstract: A probe-actuated guard-shield switch mechanism automatically disconnects a guard shield to an input terminal of a measurement instrument upon insertion of a guard probe, and reconnects the guard shield upon removal of the guard probe. The mechanism provides a break-before-make connection sequence for safety reasons, and also provides a non-conductive safety gate to minimize shock hazard.