Abstract: A controller includes: a pulse-width modulation (PWM) circuit; a control loop; and a reference voltage controller. The control loop has: a feedback input adapted to be coupled to an output voltage of a power stage; a control loop output coupled to a PWM control input; and an operational amplifier with a first feedback input, a first reference input, and an amplifier output, the first feedback input connected to the feedback input, and the amplifier output coupled to the PWM control input. The reference voltage controller has a reference voltage output coupled to the first reference input, the reference voltage controller configured to adjust a reference voltage provided to the reference voltage output responsive to a dynamic error estimate based on error in the operational amplifier.

Abstract: A power converter includes a power converter circuit and a microcontroller that controls the power converter circuit. The microcontroller includes a power control unit and a processing unit. The power control unit adjusts the switching frequency of the power converter circuit based on thresholds of a resonant capacitor of the power converter circuit. The power control unit also generates event signals indicative of breaches of the thresholds by the resonant capacitor. When the processing unit receives an event signal from the power control unit indicative of a breach of one of the thresholds by the resonant capacitor, the processing unit determines whether the switching frequency falls outside a defined range based on the event signal. In response to determining that the switching frequency falls outside the defined range, the processing unit instructs the power control unit to clamp the switching frequency of the power converter circuit.

Abstract: Systems and methods provide for inherited access permissions, thereby facilitating read and write access by called contexts. Hardware logic may enforce access permissions in the system. When a processor core executes code associated with a first context, the processor core generates a first hardware signal identifying the first context. The processor core may then switch from the first context to the second context due to the first context calling the second context. The processor core may then generate a second hardware signal identifying the calling (first) context, and then the first hardware signal identifies the called (second) context. The hardware logic that enforces the access permissions may then determine that the second context is being called and that the second context includes either direct access permissions or inherited access permissions associated with the calling (first) context.

Abstract: An example apparatus includes an input terminal; an output terminal; a delay circuit including an input terminal and an output terminal, the input terminal coupled of the delay circuit coupled to the input terminal; a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the comparator coupled to a supply voltage terminal, the second input terminal of the comparator coupled to a reference voltage terminal; and a logic AND gate including a first input terminal, a second input terminal, a third input terminal, and an output terminal, the first input terminal of the logic AND gate coupled to the output terminal of the comparator, the second input terminal of the logic AND gate coupled to the output terminal of the delay circuit, the third input terminal of the logic AND gate coupled to the input terminal, and the output terminal of the logic AND gate coupled to the output terminal.

Abstract: A system includes a multiplexer, an input/output (I/O) pin, a logic circuit, and a control register. The multiplexer has multiple inputs, an output, and a selection input. The logic circuit is coupled between the multiplexer and the I/O pin. The logic circuit has a first input. The control register includes first and second bit fields corresponding to the I/O pin. The first bit field is coupled to the selection input of the multiplexer, and the second bit field is coupled to the first input of the logic circuit.

Abstract: An analog-to-digital converter circuit module utilizing dither to reduce multiplicative noise. A dither generation circuit generates a noise-shaped analog dither signal having lower amplitudes at frequencies below a cutoff frequency than at frequencies above the cutoff frequency. The noise-shaped analog dither signal is added to the input analog signal to be converted and the summed signal applied to an analog-to-digital converter The dither generation circuit may be implemented as an analog dither generator followed by an analog high-pass filter. The dither generation circuit may alternatively be implemented digitally, for example with a digital noise-shaping filter applying a high-pass digital filter to a pseudo-random binary sequence. The digital dither generation circuit may alternatively be implemented by one or more 1-bit sigma-delta modulators, each generating a bit of a digital dither sequence that is converted to analog.

Abstract: A system includes a multi-core shared memory controller (MSMC). The MSMC includes a snoop filter bank, a cache tag bank, and a memory bank. The cache tag bank is connected to both the snoop filter bank and the memory bank. The MSMC further includes a first coherent slave interface connected to a data path that is connected to the snoop filter bank. The MSMC further includes a second coherent slave interface connected to the data path that is connected to the snoop filter bank. The MSMC further includes an external memory master interface connected to the cache tag bank and the memory bank. The system further includes a first processor package connected to the first coherent slave interface and a second processor package connected to the second coherent slave interface. The system further includes an external memory device connected to the external memory master interface.

Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

Abstract: In described examples of a system for outputting a patterned light beam, the system includes: an illumination source; a positive optical element positioned to receive light from the illumination source and to output converging light; a reflective element positioned to receive the converging light from the positive optical element, the reflective element configured to reflect the converging light to form a scan beam; and a negative optical element to receive the scan beam from the reflective element, the negative optical element configured to output the scan beam to a field of view.

Abstract: A method is provided that includes determining a target picture virtual memory access (VMA) bandwidth rate, wherein the target picture VMA bandwidth rate indicates a maximum VMA bandwidth rate for motion compensation of a picture, and verifying the target picture VMA bandwidth rate for a compressed video bit stream.

Abstract: A synchronization circuit includes a first synchronizer having a first data input, a first clock input, and first output; a second synchronizer having a second data input, a second clock input, and a second output; selection circuitry having first, second, third and fourth inputs, and a synchronized data output, the first and second inputs coupled to the first and second outputs, respectively; and storage circuitry having a storage data input coupled to the synchronized data output, a third clock input, and a feedback output coupled to the fourth input.

Abstract: A real time, on-the-fly data encryption system is operable to encrypt and decrypt data flow between a secure processor and an unsecure external memory system. Multiple memory segments are supported, each with its own separate encryption capability, or no encryption at all. Data integrity is ensured by hardware protection from code attempting to access data across memory segment boundaries. Protection is also provided against dictionary attacks by monitoring multiple access attempts to the same memory location.

Abstract: One example described herein includes a method for fabricating integrated circuit (IC) packages. The method includes fabricating a plurality of IC dies and providing a conductive metal material sheet. The method also includes laser-cutting the conductive metal material sheet to form a lead-frame sheet. The lead-frame sheet includes at least one of through-holes and three-dimensional locking features. The method further includes coupling the IC dies to the lead-frame sheet and coupling the lead-frame sheet and the IC dies to packaging material to form an IC package block comprising the IC packages.

Abstract: An oscillator circuit includes a first BAW oscillator, a first coupling stage, a second BAW oscillator, and a second coupling stage. The first BAW oscillator is configured to generate a first output signal at a frequency. The first coupling stage is coupled to the first BAW oscillator, and is configured to amplify the first output signal. The second BAW oscillator is coupled to the first coupling stage, and is configured to generate a second output signal at the frequency. The second output signal differs in phase from the first output signal. The second coupling stage is coupled to the first BAW oscillator and the second BAW oscillator, and is configured to amplify the second output signal and drive the first BAW oscillator.

Abstract: An example semiconductor package comprises a patch antenna formed in a first conductor layer of a multilayer package substrate. The multilayer package substrate comprises conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers. The multilayer package substrate has a board side surface opposite a device side surface. The semiconductor package further comprises a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the patch antenna. An antenna horn is mounted to the device side surface and aligned with the patch antenna using a mounting structure. The semiconductor package further comprises a reflector formed on a second conductor layer in the multilayer package substrate. The second conductor layer is positioned closer to the board side surface of the multilayer package substrate compared to the patch antenna.

Abstract: In accordance with at least one example of the description, a microelectromechanical systems (MEMS) device includes a hinge. The MEMS device also includes a spring tip. Additionally, the MEMS device includes a top layer including a recessed shelf and a top surface, where the recessed shelf is coupled to the hinge.

Abstract: A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

Abstract: In some examples, an apparatus includes a delay-based frequency multiplier and an error detection circuit. The delay-based frequency multiplier has a clock input, a multiplier clock output, and a delay calibration input. The error detection circuit has a detection input and a detection output. The detection input is coupled to the multiplier clock output, and the detection output is coupled to the delay calibration input. The error detection circuit is configured to receive a clock signal at the detection input, and provide a period error signal at the detection output based on a time difference between a first edge of the clock signal and a second edge of a delayed version of the clock signal.

Abstract: A control circuit for a power factor correction (PFC) circuit, the control circuit includes a multiplier having first, second, and third multiplier inputs and a multiplier output. The control circuit has an adder having first and second inputs and an output. The first input of the adder is coupled to the multiplier output. The control circuit further includes a root mean square (RMS) calculation circuit configured to determine a square of a root mean square of an input sinusoidal voltage. The RMS calculation circuit has an output coupled to the second multiplier input. An input voltage square calculation circuit is configured to determine a square of the input sinusoidal voltage. The input voltage square calculation circuit has an output coupled to the third multiplier input.

Abstract: A method for decoding an encoded video bit stream in a video decoder is provided that includes determining a scan pattern type for a transform block to be decoded, decoding a column position X and a row position Y of a last non-zero coefficient in the transform block from the encoded video bit stream, selecting a column-row inverse transform order when the scan pattern type is a first type, selecting a row-column inverse transform order when the scan pattern type is a second type, and performing one dimensional (1D) inverse discrete cosine transformation (IDCT) computations according to the selected transform order to inversely transform the transform block to generate a residual block.