Abstract: Disclosed examples provide methods that include forming a conductive structure at least partially above a conductive feature of a wafer, attaching a solder ball structure to a side of the conductive structure, and thereafter forming a repassivation layer on a side of the wafer proximate the side of the conductive structure. Further examples provide microelectronic devices and integrated circuits that include a conductive structure coupled with a conductive feature of a metallization structure, a solder ball structure connected to the conductive structure, and a printed repassivation layer disposed on the side of the metallization structure proximate a side of the conductive structure.

Abstract: A method is provided that includes receiving a coded largest coding unit in a video decoder, wherein the coded largest coding unit includes a coded coding unit structure and a plurality of coded quantization parameters, and decoding the coded largest coding unit based on the coded coding unit structure and the plurality of coded quantization parameters.

Abstract: An ADC includes a comparator to provide a comparator output responsive to an input voltage of the ADC and a DAC output voltage; a SAR circuit including a SAR that stores an n-bit digital code that is initialized at a beginning of a conversion phase of the ADC, where the SAR circuit is to update the digital code responsive to the comparator output, where an ADC output is responsive to the digital code at an end of the conversion phase; and a DAC to provide the DAC output voltage responsive to the digital code and a reference voltage. The DAC includes an m-bit CDAC and an (n?m)-bit RDAC to provide an intermediate voltage responsive to the n?m least-significant bits of the digital code and the reference voltage. The CDAC provides the DAC output voltage responsive to the m most-significant bits of the digital code, the intermediate voltage, and reference voltage.

Abstract: A microelectronic device includes a resistive differential alignment monitor (RDAM), including a first variable-width resistor and a second variable-width resistor, which are members of a conductor level. Each of the resistors include a wide portion and a narrow portion. The RDAM further includes a vertical connector to each of the wide portion and the narrow portion of the first variable-width resistor, and to the wide portion and the narrow portion of the second variable-width resistor. The vertical connectors are members of a vertical connector level. Test terminals are coupled to the vertical connectors. The vertical connectors to the first variable-width resistor and the vertical connectors to the second variable-width resistor are separated by equal distances and are oriented anti-parallel to each other. The RDAM may be used to estimate a misalignment distance between the members of the vertical connector level and the members of the conductor level.

Abstract: A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.

Abstract: In some examples, an apparatus comprises: an amplifier having an amplifier output and first and second amplifier inputs, the first amplifier input coupled to a reference voltage terminal, and the second amplifier input coupled to a power input terminal; a ramp generation circuit having a reset input and a ramp output; a comparator having a comparator output and first and second comparator inputs, the first comparator input coupled to the amplifier output, and the second comparator input coupled to the ramp output; and a switching signal generation circuit having a circuit input and a circuit output, the circuit input coupled to the comparator output, and the circuit output coupled to a power control terminal.

Abstract: An apparatus is provided and includes a rotary encoder that comprises a stator, a rotor, and a controller. The stator has an opening adapted to surround a first portion of a rotatable shaft, a transmit region, and a receive region. The rotor has an opening adapted to surround a second portion of the rotatable shaft, an annular conductive region, and at least one conductor electrically coupled with the annular conductive region. The controller has an input coupled to the receive region and has an output coupled to the transmit region. The controller is configured to transmit a first signal on the output of the controller and to the transmit region of the stator, receive a second signal on the input of the controller and from the receive region of the stator, and determine, based on the second signal, a proximity of the at least one conductor to the receive region.

Abstract: A system includes a voltage regulator having an output voltage and a power management system, coupled to the voltage regulator. The power management system operable to determine whether the output voltage is within an active range, set the active range to a first range during a first time, or during a first mode, and set the active range to a second range for a second time, or during a second mode.

Abstract: A wafer defect detection apparatus and a method of fabricating an IC using the same. Images of a plurality of semiconductor wafers forming a wafer lot are captured at a targeted process step of a fabrication flow and preprocessed, wherein a medoid image is identified as a reference wafer image. In one arrangement, preprocessed wafer images of a semiconductor wafer lot may be analyzed for defects based on an ensemble of image analysis techniques using at least one of the reference wafer image from the wafer lot and a template patch to enhance the predictive power of defect detection.

Abstract: Methods, apparatus, systems and articles of manufacture to compensate radar system calibration are disclosed. A radio-frequency (RF) subsystem having a transmit channel, a receive channel, and a loopback path comprising at least a portion of the transmit channel and at least a portion of the receive channel, a loopback measurer to measure a first loopback response of the RF subsystem for a first calibration configuration of the RF subsystem, and to measure a second loopback response of the RF subsystem for a second calibration configuration of the RF subsystem, and a compensator to adjust at least one of a transmit programmable shifter or a digital front end based on a difference between the first loopback response and the second loopback response to compensate for a loopback response change when the RF subsystem is changed from the first calibration configuration to the second calibration configuration.

Abstract: A method of entropy coding in a video encoder is provided that includes assigning a first bin to a first single-probability bin encoder based on a probability state of the first bin, wherein the first single-probability bin encoder performs binary arithmetic coding based on a first fixed probability state, assigning a second bin to a second single-probability bin encoder based on a probability state of the second bin, wherein the second single-probability bin encoder performs binary arithmetic coding based on a second fixed probability state different from the first fixed probability state, and coding the first bin in the first single-probability bin encoder and the second bin in the second single-probability bin encoder in parallel, wherein the first single-probability bin encoder uses a first rLPS table for the first fixed probability state and the second single-probability bin encoder uses a second rLPS table for the second fixed probability state.

Abstract: A method for interconnecting bond pads of semiconductor dies or devices with corresponding leads in a lead frame with printed conductive interconnects in lieu of bond wires and an apparatus resulting from the above method. More specifically, some examples include printing an insulating foundation path from bond-pads on a semiconductor die to leads of a lead frame to which the semiconductor die is attached. A foundation conductive trace is printed on top of the insulating foundation path from each bond pad on the die to a corresponding lead of the lead frame. Optionally, on top of the conductive trace, a cover insulating cover layer is applied on exposed portions of the conductive interconnects and the foundation insulating layer. Preferably, this can be the same material as foundation layer to fully adhere and blend into a monolithic structure, rather than separate layers. Optionally, a protective layer is then applied on the resulting apparatus.

Abstract: A circuit includes a first transistor comprising a first control input and first and second current terminals, the first control input coupled to receive a first input control signal, and the first current terminal coupled to a first power supply node. The circuit also includes a first resistor coupled to the first control input of the first transistor, a first capacitor coupled between the second current terminal of the first transistor and the first resistor and a second transistor comprising a second control input and third and fourth current terminals, the third current terminal coupled to the first resistor and to the first capacitor.

Abstract: Simplified communication between user equipment and a neighboring cell not the primary cell is achieved by restricting the transmission parameters, such as bandwidth, of the neighboring cell transmission and provision of a simplified secondary baseband processor in the user equipment.

Abstract: A communication circuit includes network formation circuitry configured to establish a wireless network between a primary wireless transceiver and a secondary wireless transceiver. The communication circuit also includes data transfer circuitry configured to perform data transfers between the primary wireless transceiver and the secondary wireless transceiver. The communication circuit further includes resynchronization circuitry configured to resynchronize the secondary wireless transceiver with the established wireless network within a target time interval.

Abstract: A wireless network with network-level channel hopping. A wireless network includes a wireless device. The wireless device includes a receiver, a data channel selector, and a transmitter. The receiver is configured to receive a beacon signal comprising a beacon sequence value. The data channel selector is configured to select, as a pseudorandom function of the beacon sequence value, a data channel on which to transmit in an interval following reception of the beacon signal. The transmitter is configured to transmit on the data channel selected by the channel selector.

Abstract: A driver includes a low-resistance charging path between a supply voltage rail and a first output node, a high-resistance charging path between the supply voltage rail and the first output node, an inverter coupled to the first output node and configured to enable and disable the low-resistance charging path, and a high-resistance discharging path between the first output node and a second output node. The first output node is coupled to a control terminal of a pass gate transistor in some implementations. The low-resistance charging path charges a voltage on the first output node to a threshold voltage of the pass gate transistor, and the high-resistance charging path charges the voltage on the first output node greater than the threshold voltage of the pass gate transistor. The high-resistance discharging path discharges the voltage on the first output node.

Abstract: A method for encoding a video sequence in a scalable video encoder to generate a scalable bitstream is provided that includes encoding the video sequence in a first layer encoder of the scalable video encoder to generate a first sub-bitstream, encoding the video sequence in a second layer encoder of the scalable video encoder to generate a second sub-bitstream, wherein portions of the video sequence being encoded in the second layer encoder are predicted using reference portions of the video sequence encoded in the first layer encoder, combining the first sub-bitstream and the second sub-bitstream in the scalable bitstream, and signaling an indication of a highest temporal level of the first sub-bitstream comprising at least one of the reference portions in the scalable bitstream.

Abstract: Aspects of the disclosure provide for an apparatus. In some examples, the apparatus includes a clock generator, a clock data recovery (CDR) circuit, a state machine, and an adder. The clock generator is configured to determine a sampling clock based on a received input clock and a clock offset. The CDR circuit is configured to determine a phase of the input clock and determine CDR codes based on the determined phase and sampled data. The state machine is configured to record a first CDR code of the CDR codes at a first time, record a second CDR code of the CDR codes at a second time subsequent to the first time, and determine a calibrated offset based on the first CDR code and the second CDR code. The adder is configured to determine the clock offset according to the CDR codes and the calibrated offset.

Abstract: A method and apparatus for encoding bit code utilizing context dependency simplification to reduce dependent scans. The method includes retrieving at least one 2 dimensional array of transform coefficient, transforming the at least one 2 dimensional array of transform coefficient to a 1 dimensional coefficient scanning using a diagonal scan in a fixed direction, utilizing the at least one 1 dimensional array of transform coefficients for context selection based on fewer than 11 neighbors, potentially selected based on scan direction, slice type, coding unit type and binarization, and performing arithmetic coding to generate coded bit utilizing context selection and binarization.