Abstract: In some examples, a semiconductor device comprises a substrate, a trench, and a layer of a dielectric material. The substrate includes a semiconductor material and has opposing first and second surfaces. The trench extends between the first surface and the second surface, the trench having the dielectric material. The layer of the dielectric material is on the second surface of the substrate and is contiguous with the dielectric material in the trench.

Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

Abstract: In an example, a system includes a phase frequency detector (PFD) coupled to a charge pump, and a loop filter coupled to the charge pump. The system also includes a voltage controlled oscillator (VCO) coupled to the loop filter. The system includes a fast Fourier transform (FFT) engine coupled to an output of the VCO, the FFT engine configured to estimate a phase and a magnitude of reference spurs of an input reference signal. The system includes spur correction circuitry coupled to an input of the VCO, the spur correction circuitry configured to correct for the reference spurs of the input reference signal based at least in part on the phase and magnitude of the reference spurs.

Abstract: Described examples include an integrated circuit having a transistor with a first gate on a first gate insulating layer. The transistor also has second gate separated from the first gate by a gate gap. The integrated circuit also includes a channel well at the gate gap extending under the first gate and the second gate. The transistor has a first source in the channel adjacent to an edge of the first gate. The transistor having a second source formed in the channel adjacent to an edge of the second gate separated from the first source by a channel gap. The transistor has at least one back-gate contact, the at least one back-gate contact separated from the first gate by a first back-gate contact gap and separated from the second gate by a second back-gate contact gap.

Abstract: A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

Abstract: In described examples of an isolation device, an isolation die that has a set of bond pads is mounted on a first lead frame that has a set of leads. A portion of the bond pads are coupled to respective leads. A first mold material encapsulates the isolation device and the first lead frame forming a first package. The first package is mounted on a second lead frame that has a set of leads. A portion of the first lead frame leads is coupled to respective ones of the second lead frame leads. A second mold material encapsulates the first package and the second lead frame.

Abstract: An apparatus includes a light source configured to produce light and a prism. The apparatus also includes freeform optics optically coupled between the light source and the prism, the freeform optics configured to direct the light towards the prism and eyepiece optics optically coupled to the prism. Additionally, the apparatus includes a spatial light modulator (SLM) optically coupled to the prism, the prism configured to direct the light towards the SLM, the SLM configured to modulate the light to produce modulated light, and the prism configured to direct the modulated light towards the eyepiece optics.

Abstract: Transaction mappers, methods and systems are provided. An example transaction mapper includes a table that associates virtual identification values with bus-device-function (BDF) values; and a firewall that receives an input-output request including a first virtual identification value of the virtual identification values, the first virtual identification value being associated with a function of an external peripheral, generates a first BDF value and a first traffic class value based on the table and the first virtual identification value, determine whether the first virtual identification value satisfies a threshold range, and determine whether to forward the input-output request to an external host device based on whether the first virtual identification value satisfies the threshold range.

Abstract: Various embodiments of the present technology relate to using neural networks to detect objects in images. More specifically, some embodiments relate to the reduction of computational analysis regarding object detection via neural networks. In an embodiment, a method of performing object detection is provided. The method comprises determining, via a convolution neural network, at least a classification of an image, wherein the classification corresponds to an object in the image and comprises location vectors corresponding to pixels of the image. The method also comprises, for at least a location vector of the location vectors, obtaining a confidence level, wherein the confidence level represents a probability of the object being present at the location vector, and calculating an upper-bound score based at least on the confidence level.

Abstract: A monitoring circuit for a photovoltaic module includes a measurement conditioning circuit, a microcontroller circuit, and a transmitter circuit. The measurement conditioning circuit includes a voltage sense terminal, a voltage reference terminal, and a digital measurement data output. The microcontroller circuit includes a digital measurement data input coupled with the digital measurement data output, a modulation clock input, a measurement data stream output, and a transmit select output. The transmitter circuit includes a measurement data stream input coupled with the measurement data stream output, a modulation clock output coupled with the modulation clock input, a transmit select input coupled with the transmit select output, and positive and negative output communication terminals.

Abstract: In an example, a method includes storing code for a first central processing unit (CPU) executing a first application in a first region of a memory, and storing code for a second CPU executing a second application in a second region of the memory. The method includes storing shared code for the first CPU and the second CPU in a third region of the memory. The method includes storing read-write data for the first CPU in a fourth region of the memory and storing read-write data for the second CPU in a fifth region of the memory. The method includes translating a first address from a first unique address space for the first CPU to a shared address space in the third region, and translating a second address from a second unique address space for the second CPU to the shared address space in the third region.

Abstract: System and methods for using channel quality reports to reduce inter-band interference are disclosed. Channel information is received at a first wireless communication device from a second wireless communication device. The first wireless device is operating in a first frequency range, and the second wireless device is operating in a second frequency range. The first frequency range is adjacent to the second frequency range. A channel quality report is generated at the first wireless communication device. The channel quality report indicates that particular sub-bands in the first frequency range have low channel quality. The particular sub-bands are selected using the channel information.

Abstract: A balun includes a first winding which has a first terminal coupled to an input, and a second terminal coupled to a reference potential terminal. The balun includes a second winding magnetically coupled to the first winding. The second winding has a first terminal coupled to a first differential output, a second terminal coupled to a second differential output, and a tap coupled to the reference potential terminal. The balun includes a first capacitor which has a first terminal coupled to the first winding and a second terminal coupled to the second winding. The balun includes a third winding which has a first terminal coupled to the reference potential terminal and a floating second terminal. The balun includes a second capacitor which has a first terminal coupled to the third winding and a second terminal coupled to the second winding.

Abstract: In examples, an apparatus has input and output terminals, and includes a first transistor having a first gate, source, and drain, wherein the first source is coupled to the input terminal, and the first drain is coupled to the output terminal, a second transistor having a second gate, source, and drain, wherein the second gate is coupled to a ground terminal, and the second source is coupled to the first gate, a third transistor having a third gate, source, and drain, wherein the third gate is coupled to an enable terminal, the third source is coupled to the ground terminal, and the third drain is coupled to the second drain, and a fourth transistor having a fourth gate, source, and drain, wherein the fourth gate is coupled to the second drain, the fourth source is coupled to the second source, and the fourth drain is coupled to the input terminal.

Abstract: In examples, a semiconductor package comprises a substrate and multiple columns of semiconductor dies positioned approximately in parallel along a length of the substrate. The package also includes multiple passive components positioned between the multiple columns of semiconductor dies, the multiple passive components angled between 30 and 60 degrees relative to the length of the substrate, a pair of the multiple passive components having a gap therebetween that is configured to permit mold compound flow through capillary action. The package also includes a mold compound covering the substrate, the multiple columns of semiconductor dies, and the multiple passive components.

Abstract: Various embodiments disclosed herein relate to defective pixel detection and correction, and more specifically to using threshold functions based on color channels to compare pixel values to threshold values. A method is provided herein that comprises identifying a color channel of an image pixel in a frame and identifying a threshold function based at least on the color channel. The method further comprises applying the threshold function to one or more nearest-neighbor values to obtain a threshold value and determining whether a corresponding sensor pixel is defective based at least on a comparison of the image pixel to the threshold value.

Abstract: Disclosed herein are improvements to pixel pattern conversion, upsampling, and IR decontamination processes. An example includes an image processing pipeline comprising an upstream component, a pattern conversion component downstream with respect to the upstream component in the image processing pipeline, and a downstream component relative to the pattern conversion component. The pattern conversion component is configured to obtain RGB-IR pixel data produced by the upstream component of the image processing pipeline and convert the RGB-IR pixel data into RGB pixel data and IR pixel data using a conversion engine. The conversion engine is configured to demosaic the RGB-IR pixel into the RGB pixel data and the IR pixel data, remosaic the RGB pixel data into an RGB pattern and the IR pixel data into an IR pattern and remove IR contamination from the RGB pixel data of the RGB pattern for use by the downstream component.

Abstract: An IC is coupled to a power stage having a first half bridge having first and second transistors and a second half bridge having third and fourth transistors. A controller has a first control output to provide first-fourth control signals to the first-fourth transistors. The controller asserts the first-fourth control signals to implement a state sequence. The state sequence includes a first state in which the first and fourth transistors are ON, a second state in which the first and third transistors are ON, a third state in which the second and fourth transistors are ON, and a fourth state in which the second and third transistors are ON. During each switching cycle, the controller implements the first and fourth states with one of the second or third states implemented between the first and fourth states, with every n switching cycles alternating implementation of the second or third states.

Abstract: An example apparatus includes: bandwidth estimator circuitry configured to: obtain a first memory transaction; and determine a consumed bandwidth associated with the memory transaction; and gate circuitry configured to: permit transmission of the memory transaction to a memory controller circuitry; determine whether to gate a second memory transaction generated by a source of the first memory transaction based on the consumed bandwidth of the first memory transaction; and when it is determined to gate the second memory transaction, prevent transmission of the second memory transaction for an amount of time based on the consumed bandwidth.

Abstract: A digital data processor includes an instruction memory storing instructions specifying a data processing operation and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to perform a table write in response to a look up table initialization instruction by duplicating at least one data element from a source data register to create duplicated data elements, and writing the duplicated data elements to a specified location in a specified number of at least one table and a corresponding location in at least one other table.