Patents Assigned to Texas Instruments
  • Patent number: 11368012
    Abstract: Apparatus and method for controlling a pyro-fuse. A pyro-fuse control system includes a current sensing circuit and a diagnostic circuit. The current sensing circuit is configured to determine whether the current flowing in conductor exceeds a threshold current. The diagnostic circuit is coupled to the current sensing circuit. The diagnostic circuit is configured to determine whether an indication of current exceeding the threshold current generated by the current sensing circuit is caused by current flowing the conductor and is not caused by a fault in the current sensing circuit.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: June 21, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Taraka Rama Chandra Reddy Kambham
  • Patent number: 11368699
    Abstract: Several methods and systems for masking multimedia data are disclosed. In an embodiment, a method for masking includes performing a prediction for at least one multimedia data block based on a prediction mode of a plurality of prediction modes. The at least one multimedia data block is associated with a region of interest (ROI). A residual multimedia data associated with the at least one multimedia data block is generated based on the prediction. A quantization of the residual multimedia data is performed based on a quantization parameter (QP) value. The QP value is variable such that varying the QP value controls a degree of masking of the ROI.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: June 21, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yashwant Dutt, Kumar Desappan, Piyali Goswami
  • Patent number: 11368150
    Abstract: A device includes an output circuit configured to drive a gate of a field effect transistor (FET) in response to a drive signal. The FET includes a body diode. Control logic is configured to generate the drive signal to control the output circuit to drive the FET. A measurement circuit is configured to sample a first voltage across the FET in response to a first state of the drive signal and configured to sample a second voltage across the FET in response to a second state of the drive signal. The second state of the drive signal is different from the first state. The control logic is configured to determine a difference between the first voltage and a reference voltage. The control logic is configured to compare the difference to a degradation threshold to determine a level of degradation of the FET. The reference voltage is determined based on the second voltage.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: June 21, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gangyao Wang, Xiong Li, Suxuan Guo
  • Patent number: 11368009
    Abstract: An electronic control unit (ECU) operates between first and second voltage rails and includes an amplifier circuit and a single current sense circuit coupled to carry a signal to a bus pin and to protect the bus pin from both a short to ground and a short to battery. The single current sense circuit includes a switch circuit that passes the signal to the bus pin and a forward current sensing circuit that provides a second current that is proportional to an output current at the bus pin. The forward current sensing circuit causes the second current to be substantially zero when voltage on the bus pin is above a given value. The single current sense circuit also includes a forward current protection circuit and a reverse current switching circuit that receives the second current and closes a connection to the second voltage when the second current is zero.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: June 21, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sri Navaneethakrishnan Easwaran, Timothy Paul Duryea
  • Patent number: 11368124
    Abstract: An oscillator includes: a bulk-acoustic wave (BAW) resonator having a first BAW resonator terminal and a second BAW resonator terminal; and an active circuit coupled to the first and second BAW resonator terminals and having a series resonance topology with: a first transistor; a second transistor; a first resistor; a second resistor; a capacitive network coupled to first and second BAW resonator terminals and to respective current terminals of the first and second transistors; and an inductor having a first inductor terminal and a second inductor terminal, the first inductor terminal coupled to the capacitive network, and the second inductor terminal coupled to ground terminal.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: June 21, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sachin Kalia, Tolga Dinc, Bichoy Bahr, Swaminathan Sankaran
  • Patent number: 11368111
    Abstract: A circuit comprises a multiphase gate driver to be coupled to a multiphase inverter for driving a multiphase motor. For each phase, the multi-phase gate driver is to, in accordance with a pulse width modulation (PWM) control signal, turn on and off a high side transistor of a given pair of high and low side transistors of the multiphase inverter, discontinue the PWM control signal turn to the high side transistor of the given pair and turn off the high side transistor of the given pair, and turn on the low side transistor of the given pair until a current level through the low side transistor falls below a threshold, at which time, turn off the low side transistor.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: June 21, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Manu Balakrishnan
  • Patent number: 11366076
    Abstract: In described examples, one or more devices include: apparatus including a lens element and a transducer to vibrate the lens element at an operating frequency when operating in an activated state; and controller circuitry. The controller circuitry is arranged to measure an impedance of the apparatus, to determine an estimated temperature of the apparatus in response to the measured impedance, to compare the estimated temperature against a temperature threshold for delineating an operating temperature range of the apparatus, and to toggle an activation state of the transducer in response to comparing the estimated temperature against the temperature threshold.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: June 21, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: David Patrick Magee, Stephen John Fedigan
  • Patent number: 11368190
    Abstract: Systems and methods for designing, using, and/or implementing beacon-enabled communications for variable payload transfers are described. In various embodiments, these systems and methods may be applicable to power line communications (PLC). For example, a method may include implementing a superframe having a plurality of beacon slots, a plurality of intermediate slots following the beacon slots, and a poll-based Contention Free Period (CFP) slot following the intermediate slots. Each of the beacon slots and each of the intermediate slots may correspond to a respective one of a plurality of frequency subbands, and the poll-based CFP slot may correspond to a combination of the plurality of frequency subbands. The method may also include receiving a poll request over a first of the plurality of frequency subbands during the poll-based CFP slot, and then transmitting a data packet over a second of the plurality of frequency subbands during the poll-based CFP slot.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: June 21, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Kumaran Vijayasankar, Ramanuja Vedantham, Badri N. Varadarajan, Anand G. Dabak
  • Patent number: 11368089
    Abstract: Described systems, methods, and circuitries use an interleaved multi-level converter to convert an input signal received at an input node into an output signal at an output node. In one example, a power conversion system includes a first multi-level switching circuit, a second multi-level switching circuit, and a control circuit. The first multi-level switching circuit and the second multi-level switching circuit are coupled to a switching node, the input node, and a reference node. The control circuit is configured to generate, based on the output signal, switching control signals as pulse width modulated signals having a duty cycle to control the output signal and provide the switching control signals to the first multi-level switching circuit and the second multi-level switching circuit.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: June 21, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sombuddha Chakraborty, Hakan Oner, Yogesh Kumar Ramadass
  • Patent number: 11367719
    Abstract: In a described example, an apparatus includes: a first metal oxide semiconductor field effect transistor (MOSFET) coupled between a first input terminal for receiving a supply voltage and an output terminal for coupling to a load, and having a first gate terminal; an enable terminal coupled to the first gate terminal for receiving an enable signal; a first current mirror coupled between the first input terminal and a first terminal of a first series resistor and having an input coupled to the first gate terminal; and a second MOSFET coupled between the first gate terminal and the output terminal, and having a second gate terminal coupled to the first terminal of the first series resistor, the first series resistor having a second terminal coupled to the output terminal.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: June 21, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Qingjie Ma, Wei Xu, Jingwei Xu, Yang Wang
  • Patent number: 11368112
    Abstract: An integrated circuit includes an H-bridge circuit having a first output node for coupling to a high-side terminal of an inductor and a second output node for coupling to a low-side terminal of the inductor. A current source is coupled in series with a current sense FET between a digital upper supply voltage and the first output node, wherein during a fast decay mode, a gate of the current sense FET is coupled to be turned on. A current-sense comparator includes a first input coupled to a sensing node between the current source and the current sense FET, a second input coupled to the lower supply voltage and an output coupled to a driver control circuit.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: June 21, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ganapathi Shankar Krishnamurthy, Venkata Naresh Kotikelapudi
  • Patent number: 11366211
    Abstract: A radar system is provided that includes a radar transceiver integrated circuit (IC) configurable to transmit a first frame of chirps, and another radar transceiver IC configurable to transmit a second frame of chirps at a time delay ?T, wherein ?T=Tc/K, K?2 and Tc is an elapsed time from a start of one chirp in the first frame and the second frame and a start of a next chirp in the first frame and the second frame, wherein the radar system is configured to determine a velocity of an object in a field of view of the radar system based on first digital intermediate frequency signals generated responsive to receiving reflected chirps of the first frame and second digital IF signals generated responsive to receiving reflected chirps of the time delayed second frame, wherein the maximum measurable velocity is increased by a factor of K.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: June 21, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sandeep Rao, Karthik Subburaj, Sriram Murali, Karthik Ramasubramanian
  • Patent number: 11368650
    Abstract: A system includes a downstream facing port (DFP) coupled to a video source, an upstream facing port (UFP) coupled to a video sink, and a cable. The cable includes a first end that is connected to the DFP and a second end that is connected to the UFP. The cable is configured to carry a differential auxiliary transmission signal and detect polarity in the differential auxiliary transmission signal.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: June 21, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Charles Michael Campbell, Anwar Sadat, Mark Edward Wentroble
  • Patent number: 11366216
    Abstract: Systems and methods of measuring distance between two wireless devices by combining phase shift and time-of-flight measurements. A first wireless devices sends a first packet to the second wireless device. After receiving the first packet, the second wireless device sending to the first wireless device a second packet. After sending the second packet, the second wireless device sends a first continuous wave signal to the first wireless device. After receiving the first continuous wave signal, the first wireless device sends to the second wireless device a second continuous wave signal. The first wireless device then calculates a time-of-flight measurement based on a time between the first wireless device sending the first packet and receiving the second packet, and calculates a second measurement based on a phase shift of the first continuous wave signal and the second continuous wave signal, and combines the two measurements.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: June 21, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Tomas Motos, Espen Wium
  • Patent number: 11366715
    Abstract: A device includes a first component having a data input and a data output. The deice further includes an error correction code (ECC) generation circuit having an input coupled to the data input of the first component. The ECC generation circuit has an output. A second component has a data input coupled to the output of the ECC generation circuit. The second component has a data output. An ECC error detection circuit has a first data input coupled to the data output of the first component, and a second data input coupled to the data output of the second component.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: June 21, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Desmond Fernandes, Indu Prathapan, Jasbir Singh, Prathap Srinivasan, Rishav Karki
  • Patent number: 11367699
    Abstract: A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: June 21, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroyuki Sada, Shoichi Iriguchi, Genki Yano, Luu Thanh Nguyen, Ashok Prabhu, Anindya Poddar, Yi Yan, Hau Nguyen
  • Publication number: 20220189954
    Abstract: The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.
    Type: Application
    Filed: December 10, 2020
    Publication date: June 16, 2022
    Applicant: Texas Instruments Incorporated
    Inventors: Mahalingam Nandakumar, Brian Edward Hornung
  • Publication number: 20220189898
    Abstract: A method of forming a semiconductor device with a metal pillar overlapping a first top metal interconnect and a second top metal interconnect is disclosed. The metal pillar overlapping the first top metal interconnect and second top metal interconnect is connected to the first top metal interconnect by top metal vias while the second top metal interconnect does not contain top metal vias and remains free of a direct electrical connection to the metal pillar. The metal pillars are attached directly to top metal vias without a bond pad of metal. The elimination of the bond pad layer reduces the mask count, processing, and cost of the device. In addition, the elimination of the bond pad results in reduced die area requirements for the metal pillar.
    Type: Application
    Filed: December 16, 2020
    Publication date: June 16, 2022
    Applicant: Texas Instruments Incorporated
    Inventor: Manoj Kumar Jain
  • Publication number: 20220187378
    Abstract: An electronic device includes an ADC, a multiplexer, a voltage reference circuit, an analog circuit, and a digital circuit. The ADC has a signal input, a reference input, and an output. The multiplexer has signal inputs and a signal output coupled to the signal input of the ADC. The voltage reference circuit has an output coupled to the reference input of the ADC, a first strain sensor coupled to a first signal input of the multiplexer, a second strain sensor coupled to a second signal input of the multiplexer, and a temperature sensor. The analog circuit has an input coupled to a battery, and an output coupled to a fourth signal input of the multiplexer. The digital circuit is coupled to the output of the ADC and stores correction parameters for correcting a converted battery voltage value from the ADC.
    Type: Application
    Filed: July 30, 2021
    Publication date: June 16, 2022
    Applicant: Texas Instruments Incorporated
    Inventors: Jose Antonio Vieira Formenti, Michael Szelong, Takao Oshida, Tobias Bernhard Fritz, Vishnu Ravinuthula
  • Publication number: 20220190148
    Abstract: A semiconductor device includes a GaN FET on a silicon substrate and a buffer layer of III-N semiconductor material, with a columnar region, a transition region surrounding the columnar region, and an inter-columnar region around the transition region. The columnar region is higher than the inter-columnar region. The GaN FET includes a gate of III-N semiconductor material with a thickness greater than twice the vertical range of the top surface of the buffer layer in the columnar region. A difference between the gate thickness over the columnar region and over the transition region is less than half of the vertical range of the top surface of the buffer layer in the columnar surface. The semiconductor device may be formed by forming a gate layer of III-N semiconductor material over the barrier layer by a gate MOVPE process using a carrier gas that includes zero to 40 percent hydrogen gas.
    Type: Application
    Filed: December 15, 2020
    Publication date: June 16, 2022
    Applicant: Texas Instruments Incorporated
    Inventors: Tatsuya Tominari, Nicholas Stephen Dellas, Qhalid Fareed