Abstract: A test structure for measuring strain in the channel of transistors. A method of correlating transistor performance with channel strain.

Abstract: Methods to implement power control in a digital power amplifier are described.

Abstract: Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high power and high efficiency radio frequency power amplifier to be realized using multiple low voltage CMOS transistors or micro power amplifiers. The power combiner may be printed on a package substrate and realized either using single layer substrate through edge coupling or multiple layers substrate through broadside coupling. The micro power amplifiers may be fabricated using low voltage CMOS technology and electrical connections between the outputs from the micro power amplifiers and the power combiner may be provided through stud bumps in a flip chip technology. With the tunable matching circuits, the present invention allows the narrow band power combiner to be tuned to different frequencies.

Abstract: A low bandwidth signal path is added to copy internal node DC signal to output node. Therefore, for a DC or low frequency signal, the output signal is controlled by this loop. On the other hand, a high frequency signal is not affected because of the low-bandwidth of added loop. Thus, both DC and AC coupling modes are realized for components such as low-voltage video drivers.

Abstract: A system and are described as to adjusting voltages in a memory device, while the device is in sleep mode, to prevent or minimize voltage or current leakage of the device.

Abstract: A method and system are described for a two step precharging of bitlines in a memory array. In the first step a partial precharge of the bitline is accomplished with a lower power supply, the second step completes the bitline precharge with the higher power supply. Since the higher power supply must ultimately supply the final bitline precharge voltage achieving a partial bitline precharge with a lower power supply will result in lower sram and system power.

Abstract: A system and are described as to adjusting voltages in a memory device, while the device is in sleep mode, to prevent or minimize voltage or current leakage of the device.

Abstract: Disclosed herein are systems and methods for stacking passive component devices on a substrate. A conductive material is printed onto a first substrate using a fluid ejection device to form a printed passive device according to a predetermined design. The first substrate is attached to a second substrate, such as a die, to form a component for performing a predetermined function. The component may then be tested to determine whether the component formed according to the predetermined design performs the predetermined function. The design may be adjusted in response to the test to improve the performance of the component in performing the predetermined function. Multiple substrates having printed passive devices may be stacked and electrically connected to the die or other substrate in order to increase the number of devices formed on a particular area of that die or other substrate.

Abstract: In a described implementation of inductance enhancement by magnetic material introduction, a substrate that supports an inductive element has magnetic material introduced thereto.

Abstract: A method and system for treating a substrate using a ballistic electron beam is described, whereby the radial uniformity of the electron beam flux is adjusted by modulating the source radio frequency (RF) power. For example, a plasma processing system is described having a first RF power coupled to a lower electrode, which may support the substrate, a second RF power coupled to an upper electrode that opposes the lower electrode, and a negative high voltage direct current (DC) power coupled to the upper electrode to form the ballistic electron beam. The amplitude of the second RF power is modulated to affect changes in the uniformity of the ballistic electron beam flux.

Abstract: A method is provided for ferroelectric layer testing. An adhesion layer is deposited over a semiconductor substrate to be of a phase pure material lacking a first material. A lower electrode is deposited over the adhesion layer and a ferroelectric layer is deposited over the lower electrode. The ferroelectic layer contains the first material. The ferroelectric layer is x-rayed and the x-ray fluorescence from the ferroelectric layer is detected for characterizing the ferroelectric layer.

Abstract: A method of forming a plurality of integrated circuit die on a semiconductor wafer (30). The method forms a first integrated circuit die (32a) in a first area in a fixed position relative to the semiconductor wafer, by forming at least two devices (42a) in the first area, the at least two devices selected from a group of active and passive devices, and by forming a first metal layer (62) comprising portions connecting to the at least two devices in the first area. The method also forms a second integrated circuit die (32b) in a second area in a fixed position relative to the semiconductor wafer, the second area separated from the first area by a scribe area (34). The formation of the second integrated circuit die comprises the steps of forming at least two devices (42b) in the second area, the at least two devices selected from a group of active and passive devices, and forming the first metal layer to further comprise portions connecting to the at least two devices in the second area.

Abstract: The present invention includes forming gate structures having a nitride cap on the substrate. An ion implantation is used to dope ions into the substrate to form the lightly doped drain (LDD) structures. An oxide layer is formed on the gate structures. Subsequently, the oxide layer is etched back to form oxide spacers on the side walls of the gate structures. Next, an ion implantation with a tilted angle relative to the normal line of the substrate is used. The tilted angle is about 30 to 90 degrees respect to the substrate. The ions pass through the spacers, gate oxide and into the substrate under a portion of the gate by controlling the energy of the ion implantation. The spacers also doped with ions during the implantation. The energy of the ion implantation is about 5 to 150 KeV, and the dosage of the ion implantation is about 5E12 to 2E15 atoms/cm.sup.2. The cap silicon nitride layer is then removed.

Abstract: The double-stair-like capacitor formed on a semiconductor substrate includes a first storage node having stair-like structures in cross section view to increase the area of the first storage node. A dielectric layer substantially conformally covers a surface of the first storage node. A second storage node having a surface substantially conformally contacts the dielectric layer.

Abstract: A phase shifting mask is used for manufacturing a semiconductor integrated circuit device including a conductor pattern in which the line width of patterned conductor strips or the space between patterned conductor strips is not constant. For main transparent areas in the mask corresponding to the conductor pattern, auxiliary pattern segments are provided for compensating changes in the phase distribution of transmitted light caused by changes of the line width or the space. Alternately, the spaces between the conductor strips are adjusted to suppress the changes in the phase distribution of transmitted light. Whether the auxiliary pattern segments should have the phase shifting function is determined depending upon the disposition of the main transparent areas.

Abstract: The invention discloses a method for forming solder (114) on a substrate (112). The method includes forming a decal (110) with a plurality of solder regions (113). The method further comprises aligning the decal (110) with the substrate (112) and transferring the solder regions (113) on the decal (110) to the substrate (112).

Abstract: A three-dimensional semiconductor circuit assembly wherein each of several circuit chips is provided with patterned metal layers that extend from the circuit surface onto an edge side of the chip, then the chips are adhesively bonded to opposite surfaces of one or more dielectric spacers, respectively, whereby the edge sides of the resulting multiple-chip stack are readily connected to metal patterns on a substrate.

Abstract: A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).

Abstract: An address generator (120) forms a selective merge of two addresses. First (610) and second (620) address units generate respective first and second N bit address. Each unit (610, 620) preferrably includes a set of base address registers (611), a set of index address registers (612) and a full adder (615). Each address unit (610, 620) selects one of the base address registers (611) and one of the index address registers (612) according to the current instruction. The full adder (615) selectively adds the index address to the base address or subtracts the index address from the base addess according to the current instruction. An address multiplexer register (630) stores an N bit multiplex word.

Abstract: A method is provided for accessing data stored in memory (76). First data appearing at outputs (102) of memory (76) are read during a first reading cycle in a sequence of reading cycles, the first data retrieved from a first location in memory (76) corresponding to a first address. At the end of the first reading cycle, the first address is stepped to produce a second address corresponding to a second location in memory (76). During an idle period following the first reading cycle and prior to a second reading cycle occurring next in the sequence of reading cycles, second data is prefetched from the second location in memory (76) such that the second data appears at the bitlines (102) of memory (76) at the start of the second reading cycle.