Abstract: An apparatus an apparatus includes a light source and freeform optics optically coupled to the light source. The apparatus also includes a spatial light modulator (SLM) optically coupled to the freeform optics and a prism optically coupled between the freeform optics and the SLM. Additionally, the apparatus includes eyepiece optics optically coupled to the prism.

Abstract: Devices, systems and techniques for implementing freedom from interference (FFI) access rules. In an example, a device includes a set of primary components, a set of secondary components, and an interconnected coupled between the two sets of components. Each primary component of the set of primary components has an access identifier, among multiple access attributes, and an access attribute, among multiple access modes. Each secondary component of the set of secondary components is protected by a firewall. Each firewall is configured to specify, for each specific combination of an access identifier and access attribute, whether access to the associated secondary component is permitted and what type of access is permitted.

Abstract: An integrated circuit (IC) includes a signal detection circuit having a signal detection circuit input and a signal detection circuit output. The IC further includes a reference voltage circuit having a reference voltage circuit input and a reference voltage circuit output. The IC also includes a comparator having a first comparator input and a second comparator input. The first comparator input is coupled to the reference voltage circuit output, and the second comparator input is coupled to the signal detection circuit output. The IC includes a clamp circuit having a clamp circuit input and a clamp circuit output. The clamp circuit input is coupled to the signal detection circuit, and the clamp circuit output is coupled to the reference voltage circuit output.

Abstract: Example systems, apparatus, articles of manufacture, and methods are disclosed to implement a single-wire interface protocol to synchronize device states between multiple devices. Example logic circuitry disclosed herein for a first device includes transmit circuitry configured to pull a terminal of the first device to a first logic value for a first duration corresponding to a first command to be communicated via the terminal, wherein the first duration is one of a plurality of at least three possible durations corresponding respectively to a plurality of possible commands including the first command, and the plurality of possible commands is associated with device operation states synchronized between the first device and a second device coupled to the terminal. The example logic circuitry also includes receive circuitry configured to monitor the terminal.

Abstract: An IC, comprising a first rail supply, a second rail supply, an external pad coupled to one of the first rail supply and the second rail supply, and an ESD protection circuit coupled to the external pad. The ESD protection circuit includes a slew rate detector coupled to the external pad, an amplifier coupled to an output of the slew rate detector, a one-shot coupled to an output of the amplifier, and a clamp circuit coupled an output of the one-shot.

Abstract: A device (e.g., a BLUETOOTH device) includes memory and one or more processors coupled to the memory. The one or more processors are configured to implement a BLUETOOTH host, a BLUETOOTH host-controller interface, and a BLUETOOTH controller. The one or more processors are further configured to cause the BLUETOOTH controller to receive, from the BLUETOOTH host via the BLUETOOTH host-controller interface, a message indicating first channel and timing information for sending data corresponding to a BLUETOOTH application. The one or more processors are further configured to cause the BLUETOOTH controller to initiate sending the data based on the first channel and timing information.

Abstract: An IC including a level shifter core circuit configured to receive an input signal at an input node from a low-voltage circuit portion configured to operate with a low voltage supply level, and to translate the input signal to an output signal at an output node, the output signal having a maximum voltage greater than the low voltage supply level; and a fail-safe circuit including first and second pull-down transistors configured to respectively connect the input node and the output node to a reference voltage rail in the event that the low voltage supply level drops below a threshold level. The fail-safe circuit may also include a supply cutoff switch configured to effectuate a gated connection to the low voltage supply level in response to detecting that it is below the threshold level.

Abstract: A semiconductor device includes a Schottky diode on a silicon-on-insulator (SOI) substrate. The Schottky diode includes a guard ring with a first guard ring segment contacting a barrier region on a first lateral side of the barrier region, and a second guard ring segment contacting the barrier region on a second, opposite, lateral side of the barrier region. The first and second guard ring segments extend deeper in the semiconductor layer than the barrier region. The Schottky diode further includes a drift region contacting the barrier region, and may include a buried layer having the same conductivity type as the barrier region, extending at least partway under the drift region. The barrier region is isolated from the substrate dielectric layer of the SOI substrate by an isolation region having the same conductivity type as the guard ring. A metal containing layer is formed on the barrier region.

Abstract: At a switch terminal of a flyback converter in a discontinuous conduction mode in a power meter, an apparatus determines a resonant frequency of the flyback converter. The apparatus determines whether the resonant frequency satisfies a condition. Through a controller, the apparatus triggers an event responsive to determining that the resonant frequency satisfies the condition.

Abstract: In an example, a system includes a receiver configured to receive a differential input signal from a quadrature amplitude modulation (QAM) transmitter at a differential interface that includes a first input and a second input. The system also includes a first switch coupled to the first input and a second switch coupled to the second input, where the first switch and second switch are configured to couple the first input and the second input to a complex mixer in a non-inverting configuration. The system includes a third switch coupled to the first input and a fourth switch coupled to the second input, where the third switch and the fourth switch are configured to couple the first input and the second input to the complex mixer in an inverting configuration. The complex mixer is configured to produce an output signal based on the non-inverting configuration and the inverting configuration.

Abstract: Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and/or bypass coded bins are provided. Rather than using only truncated unary binarization for the syntax element representing the delta quantization parameter and context coding all of the resulting bins as in the prior art, a different binarization is used and only part of the resulting bins are context coded, thus reducing the worst case number of context coded bins for this syntax element. Further, binarization techniques for the syntax element representing the remaining actual value of a transform coefficient are provided that restrict the maximum codeword length of this syntax element to 32 bits or less, thus reducing the number of bypass coded bins for this syntax element over the prior art.

Abstract: In an example, an apparatus includes a first decoder circuit having a first voltage identification (VID) analog input and a first digital output. The apparatus also includes a precharge circuit having a digital input and a first analog output, the digital input coupled to the first digital output. The apparatus also includes a second decoder circuit having a second VID analog input, a precharge analog input and a second digital output, the precharge analog input coupled to the first digital output. The apparatus also includes a multiplexer having a multiplexer output and first and second multiplexer inputs, the first multiplexer input coupled to the first digital output, and the second multiplexer input coupled to the second digital output.

Abstract: A system includes: 1) a battery configured to provide an input voltage (VIN); 2) switching converter circuitry coupled to the battery, wherein the switching converter circuitry includes a power switch; 3) a load coupled to an output of the switching converter circuitry; and 4) a control circuit coupled to the power switch. The control circuit includes: 1) a switch driver circuit coupled to the power switch; 2) a summing comparator circuit configured to output a first control signal that indicates when to turn the power switch on; and 3) an analog on-time extension circuit configured to extend an on-time of the power switch by gating a second control signal with the first control signal, wherein the second control signal indicates when to turn the power switch off.

Abstract: A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing write-memory commands that are not cached in the first sub-cache, the second sub-cache including privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a level of privilege, and wherein the second sub-cache is further configured to receive a first write memory command for a memory address associated with a first level of privilege, store, in the second sub-cache, first data associated with the first write memory command and the level of privilege associated with the cache line, receive a second write memory command for the cache line, the second write memory command associated with a second level of privilege, merge the first level of privilege with the second level of privilege, and output the merged privilege level with the cache line.

Abstract: In a described example, an apparatus includes: a semiconductor die with a component on a device side surface; a die seal surrounding the component on the device side surface; a package substrate having bond pads on a die side surface; a package substrate seal formed on the die side surface of the package substrate corresponding to the die seal on the semiconductor die; the semiconductor die flip chip mounted on the bond pads of the package substrate with solder joints connecting post connects on the semiconductor die to the bond pads of the package substrate; a mold compound seal formed by the die seal and the package substrate seal; and mold compound covering a portion of the semiconductor die, a portion of the die side of the package substrate, and contacting the mold compound seal, the mold compound spaced from the component.

Abstract: A network includes an intermediate node to communicate with a child node via a wireless network protocol. An intermediate node synchronizer in the intermediate node facilitates time synchronization with its parent node and with the child node. A child node synchronizer in the child node to facilitates time synchronization with the intermediate node. The intermediate node synchronizer exchanges synchronization data with the child node synchronizer to enable the child node to be time synchronized to the intermediate node before the intermediate node is synchronized to its parent node if the intermediate node has not synchronized to its parent node within a predetermined guard time period established for the child node.

Abstract: A semiconductor isolation package includes a leadframe that includes a plurality of leadframe leads. At least one of the plurality of leadframe leads includes a lead body having a first end that comprises an external pin portion and a second end. The lead body has a leg portion coupled to a central lead portion that is coupled to an edge bend portion. The edge bend portion is formed by a first bend on the lead body proximate the second end between the central lead portion and edge bend portion. The first bend is in the direction of the first end on the leg portion. The edge bend assists in shielding electronic fields. Other aspects are presented.

Abstract: An automatic charge/discharge circuit is presented that allows a current mirror circuit with a high capacitance to quickly and automatically charge or discharge the capacitance in order to allow for a fast start-up power supply. The charge/discharge circuit automatically stops charging or discharging as the voltage on the capacitance approached a desired steady state.

Abstract: A method for detecting a fault with a cable having a resistor divider couple to the cable. The method includes converting a first sense voltage from the resistor divider network to a first digital code, determining whether the first digital code falls within a first range of digital codes corresponding to a first fault associated with the cable, and responsive to determining that the first digital code falls within the first range of digital codes, generating an indication of the first fault.

Abstract: A streaming engine employed in a digital signal processor specifies a fixed read only data stream. Once fetched the data stream is stored in two head registers for presentation to functional units in the fixed order. Data use by the functional unit is preferably controlled using the input operand fields of the corresponding instruction. A first read only operand coding supplies data from the first head register. A first read/advance operand coding supplies data from the first head register and also advances the stream to the next sequential data elements. Corresponding second read only operand coding and second read/advance operand coding operate similarly with the second head register. A third read only operand coding supplies double width data from both head registers.