Patents Assigned to Texas Instruments
  • Publication number: 20240104361
    Abstract: In one example, a neural network processor comprises a computing engine and a post-processing engine, the post-processing engine configurable to perform different post-processing operations for a range of output precisions and a range of weight precisions. The neural network processor further comprises a controller configured to: receive a first indication of a particular output precision, a second indication of the particular weight precision, and post-processing parameters; and configure the post-processing engine based on the first and second indications and the first and second post-processing parameters. The controller is further configured to, responsive to a first instruction, perform, using the computing engine, multiplication and accumulation operations between input data elements and weight elements to generate intermediate data elements.
    Type: Application
    Filed: July 20, 2023
    Publication date: March 28, 2024
    Applicant: Texas Instruments Incorporated
    Inventors: Mahesh M Mehendale, Hetul Sanghvi, Nagendra Gulur, Atul Lele, Srinivasa BS Chakravarthy
  • Publication number: 20240103875
    Abstract: In one example, a neural network processor comprises a memory interface, an instruction buffer, a weights buffer, an input data register, a weights register, an output data register, a computing engine, and a controller. The controller is configured to: receive a first instruction from the instruction buffer; responsive to the first instruction, fetch input data elements from the memory interface to the input data register, and fetch weight elements from the weights buffer to the weights register. The controller is also configured to: receive a second instruction from the instruction buffer; and responsive to the second instruction: fetch the input data elements and the weight elements from, respectively, the input data register and the weights register to the computing engine; and perform, using the computing engine, computation operations between the input data elements and the weight elements to generate output data elements.
    Type: Application
    Filed: July 20, 2023
    Publication date: March 28, 2024
    Applicant: Texas Instruments Incorporated
    Inventors: Mahesh M Mehendale, Nagendra Gulur, Srinivasa BS Chakravarthy, Atul Lele, Hetul Sanghvi
  • Publication number: 20240103811
    Abstract: In one example, a neural network processor comprises an input data register, a weights register, a computing engine configurable to perform multiplication and accumulation (MAC) operations between input data elements of a range of input precisions and weight elements of a range of weight precisions, and a controller. The controller is configured to: receive a first indication of the particular input precision and a second indication of the particular weight precision, and configure the computing engine based on the first and second indications. The controller is also configured to, responsive to an instruction: fetch input data elements and weight elements to the computing engine; and perform, using the computing engine configured based on the first and second indications, MAC operations between the input data elements at the particular input precision and the weight elements at the particular weight precision to generate intermediate output data elements.
    Type: Application
    Filed: July 20, 2023
    Publication date: March 28, 2024
    Applicant: Texas Instruments Incorporated
    Inventors: Mahesh M Mehendale, Atul Lele, Nagendra Gulur, Hetul Sanghvi, Srinivasa BS Chakravarthy
  • Patent number: 11943162
    Abstract: A transmission of information from a secondary to a primary node occurs in a plurality of transmission instances which are logical time durations. A secondary node receives an allocation of periodic transmission instances for a scheduling request indicator (SRI) and an allocation if periodic transmission instances for a sounding reference signal (SRS). In a particular transmission instance allocated for the transmission of both SRS and SRI, the secondary node transmits the SRI without transmitting the SRS if the SRI indicates a pending scheduling request; otherwise, the secondary node transmits the SRS without transmitting the SRI.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pierre Bertrand, Zukang Shen, Jing Jiang
  • Patent number: 11940863
    Abstract: Described herein is a technology for a wakeup pattern-data stream correlation by a detector to provide a trigger condition for a microcontroller in a wakeup receiver (WuRX). For example, the detector includes a data packet layer with a plurality of index registers that are updated through sampling of data streams. A sample clock is coupled to each of the plurality of index registers to independently activate each of the plurality of index registers. A shared comparator will then compare the updated plurality of index registers to corresponding shift registers that are initialized with rotating wakeup pattern bits. Based upon a number of matching results, the detector generates a triggering signal that facilitates a low-power operating mode to a high-power operating mode change.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: March 26, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Andreas Michael Schoch, Ernst Muellner
  • Patent number: 11940891
    Abstract: A method, system, and apparatus for fault detection in a microprocessor-based system uses a serial data communication protocol for communications between a peripheral device and a controller. Peripheral device interface circuitry is adapted to intermittently receive input serial data frames from the controller using the serial communication protocol and to intermittently send output serial data frames to the controller using the serial communication protocol. Each output serial data frame includes one or more status bits representing communication status data and one or more data bits representing peripheral device data. The status bits and the data bits are serially followed by at least one fault bit that indicates whether a fault is detected during sending of the output serial data frame.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Scott Allen Monroe
  • Patent number: 11942384
    Abstract: A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Makoto Shibuya, Masamitsu Matsuura, Kengo Aoya, Hideaki Matsunaga, Anindya Poddar
  • Patent number: 11940479
    Abstract: A system for determining the leakage current of a field effect transistor over temperature includes a metal oxide semiconductor field effect transistor (MOSFET) having first and second current terminals and a control terminal, wherein the first current terminal is coupled to a current measurement device. A switch is coupled to the control terminal and to a voltage source. The switch is configured to apply a voltage between a control terminal and a current terminal of the (MOSFET) responsive to a first signal, and apply approximately zero volts to the control terminal of the (MOSFET) responsive to a second signal.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Robert Allan Neidorff, Henry Litzmann Edwards
  • Patent number: 11940918
    Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: March 26, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, Timothy David Anderson, Kai Chirca, David Matthew Thompson
  • Patent number: 11940826
    Abstract: A power control integrated circuit (IC) chip can include a direct current (DC)-DC converter that outputs a switching voltage in response to a switching output enable signal. The power control IC chip can also include an inductor detect circuit that detects whether an inductor is conductively coupled to the DC-DC converter and a powered circuit component in response to an inductor detect signal. The power control IC chip can further include control logic that (i) controls the inductor detect signal based on an enable DC-DC signal and (ii) controls the switching output enable signal provided to the DC-DC converter and a linear output disable signal provided to a linear regulator based on a signal from the inductor detect circuit indicating whether the inductor is conductively coupled to the DC-DC converter and the powered circuit component.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: March 26, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Sachin Sudhir Turkewadikar, Nitin Agarwal, Madhan Radhakrishnan
  • Patent number: 11938715
    Abstract: A microstructure comprises a plurality of interconnected units wherein the units are formed of graphene tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing graphitic carbon on the metal microlattice, converting the graphitic carbon to graphene, and removing the metal microlattice.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Luigi Colombo, Nazila Dadvand, Benjamin Stassen Cook, Archana Venugopal
  • Patent number: 11940929
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to reduce read-modify-write cycles for non-aligned writes. An example apparatus includes a memory that includes a plurality of memory banks, an interface configured to be coupled to a central processing unit, the interface to obtain a write operation from the central processing unit, wherein the write operation is to write a subset of the plurality of memory banks, and bank processing logic coupled to the interface and to the memory, the bank processing logic to determine the subset of the plurality of memory banks to write based on the write operation, and determine whether to cause a read operation to be performed in response to the write operation based on whether a number of addresses in the subset of the plurality of memory banks to write satisfies a threshold.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: March 26, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Naveen Bhoria, Timothy David Anderson, Pete Michael Hippleheuser
  • Patent number: 11942387
    Abstract: In examples, a semiconductor package comprises a wafer chip scale package (WCSP) having circuitry formed in a device side and an insulative layer above the device side. The WCSP includes one or more plated walls extending vertically to form a defined space, the one or more plated walls configured to prevent mold compound from flowing into the defined space. The WCSP includes mold compound abutting surfaces of the one or more plated walls opposing the defined space. The WCSP includes a conductive terminal coupled to the circuitry and extending from the WCSP into the defined space.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: John Carlo Cruz Molina, Julian Carlo Concepcion Barbadillo, Ray Fredric Solis De Asis
  • Patent number: 11942407
    Abstract: In some examples a method comprises forming an insulating member over a circuit on a device side of a semiconductor die, removing a portion of the insulating member to produce a cavity, and forming a seed layer on the insulating member and within the cavity. In addition, the method includes forming a conductive member on the seed layer in the cavity, wherein the conductive member comprises a plurality of layers of different metal materials. Further, the method includes removing the seed layer from atop the insulating member, outside the cavity, after forming the conductive member in the cavity such that a remaining portion of the seed layer is positioned between the conductive member and the insulating member.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey Salvacion Solas, Maricel Fabia EscaƱo
  • Patent number: 11942448
    Abstract: An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive pad having a generally planar top surface that includes a cavity having a bottom surface and sidewalls extending from the bottom surface of the cavity to the top surface of the pad. An electronic device is attached to the top surface of the electrically conductive pad. A wire bond is attached from the electronic device to the bottom surface of the cavity. A molding compound encapsulates the electronic device.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bo-Hsun Pan, Hung-Yu Chou, Chung-Hao Lin, Yuh-Harng Chien
  • Patent number: 11940909
    Abstract: An Adaptive Memory Mirroring Performance Accelerator (AMMPA) includes a centralized transaction handling block that dynamically maps the most frequently accessed memory regions into faster access memory. The technique creates shadow copies of the most frequently accessed memory regions in memory devices associated with lower latency. The regions for which shadow copies are provided are updated dynamically based on use, and the technique flexible for different memory hierarchies.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: March 26, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Sriramakrishan Govindarajan, Mihir Narendra Mody, Prithvi Shankar Yeyyadi Anantha
  • Patent number: 11943629
    Abstract: A method of operating a long term evolution (LTE) communication system on a shared frequency spectrum is disclosed. A user equipment (UE) is initialized on an LTE frequency band. A base station (eNB) monitors the shared frequency spectrum to determine if it is BUSY. The eNB transmits to the UE on the shared frequency spectrum if it is not BUSY. The eNB waits for a first time if it is BUSY and directs the UE to vacate the shared frequency spectrum after the first time.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ralf Matthias Bendlin, Anthony Edet Ekpenyong, Pierre Bertrand, Brian F. Johnson
  • Patent number: 11941399
    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream. Once fetched data elements in the data stream are disposed in lanes in a stream head register in the fixed order. Some lanes may be invalid, for example when the number of remaining data elements are less than the number of lanes in the stream head register. The streaming engine automatically produces a valid data word stored in a stream valid register indicating lanes holding valid data. The data in the stream valid register may be automatically stored in a predicate register or otherwise made available. This data can be used to control vector SIMD operations or may be combined with other predicate register data.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: March 26, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Joseph Zbiciak, Son H. Tran
  • Patent number: 11942402
    Abstract: An isolator device includes a laminate die having a dielectric laminate material with a metal laminate layer on one side of the dielectric laminate material, the metal laminate layer being a patterned layer providing at least a first plate, including a dielectric layer over the first plate that includes an aperture exposing a portion of the first plate. An integrated circuit (IC) including a substrate having a semiconductor surface includes circuitry including a transmitter and/or a receiver, the IC including a top metal layer providing at least a second plate coupled to a node in the circuitry, with at least one passivation layer on the top metal layer. A non-conductive die attach (NCDA) material for attaching a side of the dielectric laminate material is opposite the metal laminate layer to the IC so that the first plate is at least partially over the second plate to provide a capacitor.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: March 26, 2024
    Assignee: Texas Instruments Incorporated
    Inventor: Thomas Dyer Bonifield
  • Patent number: 11940930
    Abstract: Methods, apparatus, systems and articles of manufacture to facilitate atomic operation in victim cache are disclosed. An example system includes a first cache storage to store a first set of data; a second cache storage to store a second set of data that has been evicted from the first cache storage; and a storage queue coupled to the first cache storage and the second cache storage, the storage queue including: an arithmetic component to: receive the second set of data from the second cache storage in response to a memory operation; and perform an arithmetic operation on the second set of data to produce a third set of data; and an arbitration manager to store the third set of data in the second cache storage.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 26, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Naveen Bhoria, Timothy David Anderson, Pete Michael Hippleheuser