Abstract: A wafer defect detection apparatus and a method of fabricating an IC using the same. Images of a plurality of semiconductor wafers forming a wafer lot are captured at a targeted process step of a fabrication flow and preprocessed, wherein a medoid image is identified as a reference wafer image. In one arrangement, preprocessed wafer images of a semiconductor wafer lot may be analyzed for defects based on an ensemble of image analysis techniques using at least one of the reference wafer image from the wafer lot and a template patch to enhance the predictive power of defect detection.

Abstract: An ADC includes a comparator to provide a comparator output responsive to an input voltage of the ADC and a DAC output voltage; a SAR circuit including a SAR that stores an n-bit digital code that is initialized at a beginning of a conversion phase of the ADC, where the SAR circuit is to update the digital code responsive to the comparator output, where an ADC output is responsive to the digital code at an end of the conversion phase; and a DAC to provide the DAC output voltage responsive to the digital code and a reference voltage. The DAC includes an m-bit CDAC and an (n?m)-bit RDAC to provide an intermediate voltage responsive to the n?m least-significant bits of the digital code and the reference voltage. The CDAC provides the DAC output voltage responsive to the m most-significant bits of the digital code, the intermediate voltage, and reference voltage.

Abstract: A power converter includes a power converter circuit and a microcontroller that controls the power converter circuit. The microcontroller includes a power control unit and a processing unit. The power control unit adjusts the switching frequency of the power converter circuit based on thresholds of a resonant capacitor of the power converter circuit. The power control unit also generates event signals indicative of breaches of the thresholds by the resonant capacitor. When the processing unit receives an event signal from the power control unit indicative of a breach of one of the thresholds by the resonant capacitor, the processing unit determines whether the switching frequency falls outside a defined range based on the event signal. In response to determining that the switching frequency falls outside the defined range, the processing unit instructs the power control unit to clamp the switching frequency of the power converter circuit.

Abstract: A circuit includes a first transistor comprising a first control input and first and second current terminals, the first control input coupled to receive a first input control signal, and the first current terminal coupled to a first power supply node. The circuit also includes a first resistor coupled to the first control input of the first transistor, a first capacitor coupled between the second current terminal of the first transistor and the first resistor and a second transistor comprising a second control input and third and fourth current terminals, the third current terminal coupled to the first resistor and to the first capacitor.

Abstract: A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.

Abstract: A driver includes a low-resistance charging path between a supply voltage rail and a first output node, a high-resistance charging path between the supply voltage rail and the first output node, an inverter coupled to the first output node and configured to enable and disable the low-resistance charging path, and a high-resistance discharging path between the first output node and a second output node. The first output node is coupled to a control terminal of a pass gate transistor in some implementations. The low-resistance charging path charges a voltage on the first output node to a threshold voltage of the pass gate transistor, and the high-resistance charging path charges the voltage on the first output node greater than the threshold voltage of the pass gate transistor. The high-resistance discharging path discharges the voltage on the first output node.

Abstract: Systems and methods provide for inherited access permissions, thereby facilitating read and write access by called contexts. Hardware logic may enforce access permissions in the system. When a processor core executes code associated with a first context, the processor core generates a first hardware signal identifying the first context. The processor core may then switch from the first context to the second context due to the first context calling the second context. The processor core may then generate a second hardware signal identifying the calling (first) context, and then the first hardware signal identifies the called (second) context. The hardware logic that enforces the access permissions may then determine that the second context is being called and that the second context includes either direct access permissions or inherited access permissions associated with the calling (first) context.

Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

Abstract: An example apparatus includes an input terminal; an output terminal; a delay circuit including an input terminal and an output terminal, the input terminal coupled of the delay circuit coupled to the input terminal; a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the comparator coupled to a supply voltage terminal, the second input terminal of the comparator coupled to a reference voltage terminal; and a logic AND gate including a first input terminal, a second input terminal, a third input terminal, and an output terminal, the first input terminal of the logic AND gate coupled to the output terminal of the comparator, the second input terminal of the logic AND gate coupled to the output terminal of the delay circuit, the third input terminal of the logic AND gate coupled to the input terminal, and the output terminal of the logic AND gate coupled to the output terminal.

Abstract: An analog-to-digital converter circuit module utilizing dither to reduce multiplicative noise. A dither generation circuit generates a noise-shaped analog dither signal having lower amplitudes at frequencies below a cutoff frequency than at frequencies above the cutoff frequency. The noise-shaped analog dither signal is added to the input analog signal to be converted and the summed signal applied to an analog-to-digital converter The dither generation circuit may be implemented as an analog dither generator followed by an analog high-pass filter. The dither generation circuit may alternatively be implemented digitally, for example with a digital noise-shaping filter applying a high-pass digital filter to a pseudo-random binary sequence. The digital dither generation circuit may alternatively be implemented by one or more 1-bit sigma-delta modulators, each generating a bit of a digital dither sequence that is converted to analog.

Abstract: In accordance with at least one example of the description, a microelectromechanical systems (MEMS) device includes a hinge. The MEMS device also includes a spring tip. Additionally, the MEMS device includes a top layer including a recessed shelf and a top surface, where the recessed shelf is coupled to the hinge.

Abstract: An integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.

Abstract: An example apparatus includes: a pullup circuit coupled to a first USB terminal; a first pulldown circuit coupled to the first USB terminal; a second pulldown circuit coupled to a second USB terminal; a third pulldown circuit coupled to a third USB terminal; a fourth pulldown circuit coupled to a fourth USB terminal; a high-speed termination detection circuit including: a current source including a first supply terminal and a second supply terminal, the first supply terminal coupled to the first USB terminal, the second supply terminal coupled to the second USB terminal; a first comparator including a first comparator terminal and a second comparator terminal, the first comparator terminal coupled to the first USB terminal; and a second comparator including a third comparator terminal and a fourth comparator terminal, the third comparator terminal coupled to the second USB terminal; and a controller including a first control terminal and a second control terminal, the first control terminal coupled to the sec

Abstract: Methods, apparatus, systems and articles of manufacture to facilitate atomic compare and swap in cache for a coherent level 1 data cache system are disclosed. An example system includes a cache storage; a cache controller coupled to the cache storage wherein the cache controller is operable to: receive a memory operation that specifies a key, a memory address, and a first set of data; retrieve a second set of data corresponding to the memory address; compare the second set of data to the key; based on the second set of data corresponding to the key, cause the first set of data to be stored at the memory address; and based on the second set of data not corresponding to the key, complete the memory operation without causing the first set of data to be stored at the memory address.

Abstract: A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.

Abstract: An IC includes first-third power rails over a semiconductor substrate. The first rail has a first polarity different from the second and third rails. The IC includes multiple first cells on the semiconductor substrate in first and second rows. The first row is separated from the second row by the first power rail. Each first cell includes a first height and a first structure having at least one transistor. For each first cell in the first row, the first structure is entirely between the first and second rails. Further, for each first cell in the second row, the first structure is between the first and third rails. The IC includes an extension cell arranged on the semiconductor substrate in the first row. The extension cell includes a second structure having at least one transistor. A portion of the second structure extends into the second row.

Abstract: An integrated circuit (IC) includes a lower group III-N layer having a first composition over a substrate, and an upper group III-N layer having a different second composition over the lower group III-N layer. A gate electrode of a High Electron Mobility Transistor (HEMT) is located over the upper group III-N layer. First and second resistor contacts make a conductive connection to the lower group III-N layer. An unbiased group III-N cover layer is located on the upper group III-N layer in a resistor area including a high Rs 2-DEG resistor, where the unbiased group III-N cover layer is positioned between the first and second contacts.

Abstract: A method includes receiving, by a MMU for a processor core, an address translation request from the processor core and providing the address translation request to a TLB of the MMU; generating, by matching logic of the TLB, an address transaction that indicates whether a virtual address specified by the address translation request hits the TLB; providing the address transaction to a general purpose transaction buffer; and receiving, by the MMU, an address invalidation request from the processor core and providing the address invalidation request to the TLB. The method also includes, responsive to a virtual address specified by the address invalidation request hitting the TLB, generating, by the matching logic, an invalidation match transaction and providing the invalidation match transaction to one of the general purpose transaction buffer or a dedicated invalidation buffer.

Abstract: Methods for operating two or more analog-to-digital converters (ADCs) are presented herein. The method may be implemented in an integrated circuit. The integrated circuit may include a first ADC and a second ADC disposed on a single semiconductor die. The integrated circuit may also include logic circuitry operably coupled to the first and second ADCs. For a digital value obtained by conversion, by the first ADC, of a first analog signal sampled by the first ADC during a period of time overlapping with another period of time during which a second analog signal is being converted by the second ADC, the logic circuitry may be configured to cause the digital value to be marked as noisy.

Abstract: A system and method for phase and gain calibration of a current sensor system. The system comprises a microcontroller configured to execute software in an energy measurement component and a calibration computer having a calibration application. The energy measurement component receives first and second digital signals representing current and voltage signals, respectively, received from a test source, and calculates active power and a power factor, and provides those values to the calibration computer. The power factor is converted to a converted phase angle. Based on the information received from the energy measurement component, the calibration application calculates parameters used to update components within the microcontroller to maximize the accuracy of the current sensor system.