Abstract: A switch-mode power supply and a zero current detector for use therein. A zero current detector includes an input stage and an output stage. The output stage is coupled to the input stage. The output stage includes a detector output terminal, a first transistor, and a second transistor. The first transistor includes an input terminal and a control terminal. The input terminal is coupled to the detector output terminal. The control terminal is coupled to the input stage. The second transistor includes an input terminal, a control terminal, and an output terminal. The input terminal is coupled to the control terminal of the first transistor. The control terminal is coupled to the input terminal of the second transistor. The output terminal is coupled to ground.

Abstract: A vehicular battery management system (BMS) comprises a battery controller, a set of battery cells, a primary network node coupled to the battery controller, and a secondary network node coupled to the set of battery cells. The primary and secondary network nodes are configured to wirelessly communicate with each other using frames that share a common frame format. The frame format includes one or more bits and a status of the one or more bits indicates whether the secondary network node is to communicate with the primary network node on behalf of another secondary network node.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for multi-banked victim cache with dual datapath. An example cache system includes a storage element that includes banks operable to store data, ports operable to receive memory operations in parallel, wherein each of the memory operations has a respective address, and a plurality of comparators coupled such that each of the comparators is coupled to a respective port of the ports and a respective bank of the banks and is operable to determine whether a respective address of a respective memory operation received by the respective port corresponds to the data stored in the respective bank.

Abstract: A technique for power aware event scheduling including receiving, from a wireless access point, an indication of a scheduled reference event, determining, for an application event, an amount of time to generate data for a wireless uplink transmission associated with the application event, receiving timing information, the timing information indicating an amount of time to divide the generated data into data frames, determining an adjusted time based on the amount of time to generate data, the received timing information, and the scheduled reference event, triggering the application event at the adjusted time, and transmitting the data frames based on the scheduled reference event.

Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.

Abstract: Address resolution information acquisition (ARIA) for a computing device is described. In some examples, ARIA includes a computing device (e.g., an Internet of things (IoT) node, a gateway, a server) determining, without use of an address resolution protocol (ARP), address resolution information of one or more other computing devices (e.g., a IoT node, a gateway, a server). In one example, the computing device uses data flowing to or from its application layer, transport layer, or network layer to determine address resolution information of another computing device. The address resolution information can comprise one or more of a link layer address (e.g., a media access control (MAC) address) and an Internet layer address (e.g., an Internet protocol (IP) address). Usage of a cache for storing or deleting address resolution information can also be part of ARIA.

Abstract: In a circuit for DC-DC voltage converters, an amplifier has first and second inputs coupled to a reference voltage terminal and an output voltage terminal, respectively. A comparator has first and second inputs coupled to an amplifier output and a switching terminal, respectively. A logic circuit has inputs coupled to the comparator output and a clock terminal. A driver circuit has first and second inputs coupled to first and second logic outputs, respectively. A first transistor having a first control terminal coupled to the first driver output is coupled between a supply voltage terminal and the switching terminal. A second transistor is coupled between the switching terminal and a ground terminal, and has a second control terminal coupled to the second driver output. A threshold detection circuit is configured to provide a threshold signal responsive to a current through the second transistor crossing a current threshold.

Abstract: An integrated circuit (IC) package comprises a semiconductor die having a first surface with a Hall-effect sensor circuit and a second surface. A plurality of through substrate vias (TSV) each having a metal layer extend from the first surface of the semiconductor die to the second surface. The IC package includes a portion of a leadframe having a first set of leads and a second set of leads. The first set of leads provide a field generating current path for directing a magnetic field toward the Hall-effect sensor circuit. The second set of leads are attached to bond pads on the semiconductor die. A first side of an insulator is attached to the leadframe using a die attach material, and a second side of the insulator is attached to the first side of the semiconductor die using a bonding material.

Abstract: A method includes determining by a primary node a network formation process to establish a network with a secondary node according to a network condition of the primary node and the secondary node, the secondary node previously paired to the primary node in a previously established network connection between the primary node and the secondary node, performing by the primary node a scanning phase as part of the network formation process with the secondary node according to network configuration information stored by the primary node and the secondary node and obtained by the primary node and the secondary node in the previously established network connection; and skipping by the primary node a pairing phase of the network formation process with the secondary node responsive to the secondary node being previously paired to the primary node in the previously established network connection.

Abstract: An integrated circuit device (100) and method comprising an IC chip (102) having metal interconnect levels (M1-Mn) including a last copper interconnect level (Mn) and a chip-to-package interconnect (110) overlying and connected to the last copper interconnect level (Mn). The chip-to-package interconnect (110) having a via (112) connected to a first element (306a) of the last copper interconnect level (Mn) and a copper conductive structure (118) (e.g., bump copper). The via (112) includes a barrier material (112a) and a tungsten fill layer (112b), the via coupled between the copper conductive structure (118) and the first element (306a).

Abstract: In at least one example, an apparatus includes a current sense circuit, an imbalance detector, and a current balancer. The current sense circuit including a first phase input, a second phase input, a first sense output, and a second sense output. The imbalance detector having a detector output, a first detector input, and second detector input. The first detector input is coupled to the first sense output and the second detector input is coupled to the second sense output. The current balancer having a balancer input and a balancer output. The balancer input is coupled to the detector output.

Abstract: Disclosed herein are systems and methods for executing multiple instruction set architectures (ISAs) on a singular processing unit. In an implementation, a processor that includes a first decoder, a second decoder, instruction fetch circuitry, and instruction dispatch circuitry is configured to execute two separate instruction set architectures. In an implementation, the instruction fetch circuitry is configured to fetch instructions from an associated memory. In an implementation the instruction dispatch circuitry is coupled to the instruction fetch circuitry, the first decoder, and the second decoder and is configured to route instructions associated with a first ISA to the first decoder, and route instructions associated with a second ISA to the second decoder.

Abstract: A de-blocking filter includes a reconstructed memory that is configured to store reconstructed pixels corresponding to a current macroblock of a video image to be filtered. The current macroblock includes a set of sub-blocks, each sub-block having horizontal edges and vertical edges. An internal pixel buffer in the de-blocking filter is configured to store pixels corresponding to the set of sub-blocks from the reconstructed memory, and to store partially filtered pixels corresponding to a set of partially filtered macroblocks. An edge order controller in the de-blocking filter is configured to load the pixels corresponding to the set of sub-blocks into a filter engine from the internal pixel buffer, to filter the set of sub-blocks, such that, at least one horizontal edge is filtered before filtering all vertical edges of the set of sub-blocks.

Abstract: A system including at least one processor configured to determine a command pattern and a projector coupled to the at least one processor. The projector is configured to project an opening pattern, project the command pattern after projecting the opening pattern, and project a closing pattern after projecting the command pattern.

Abstract: A method for determining coding unit (CU) partitioning of a largest coding unit (LCU) of a picture is provided that includes computing a first statistical measure and a second statistical measure for the LCU, selecting the LCU as the CU partitioning when the first statistical measure does not exceed a first threshold and the second statistical measure does not exceed a second threshold, and selecting CUs in one or more lower layers of a CU hierarchy of the LCU to form the CU partitioning when the first statistical measure exceeds the first threshold and/or the second statistical measure exceeds the second threshold.

Abstract: In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.

Abstract: Excessive latencies and power consumption are avoided when a large number of leaf nodes (LNs) contend simultaneously to join a time slotted channel hopping wireless communication network having a root node (RN) interfaced to LNs by one or more intermediate nodes (INs). A first plurality of shared transmit/receive slots (STRSs) is allocated for at least one IN, and a second plurality of STRSs is advertised for use by contending LNs, where the first plurality is larger than the second plurality. When a LN joins, its STRSs are re-defined such that most become shared transmit-only slots (STOSs) and no STRSs remain. The numbers of STRSs allocated to INs may vary inversely with their hop counts from the RN. One or more STOSs may be added for each of one or more INs in response to a predetermined network condition.

Abstract: A method of dicing a wafer includes positioning the wafer with its top side on a tape material. The wafer includes a plurality of die separated by scribe streets. A first pass being a first infrared (IR) laser beam is directed at the bottom side with a point of entry within the scribe streets. The first IR laser beam is focused with a focus point embedded within a thickness of the wafer, and has parameters selected to form an embedded crack line within the wafer. The embedded crack line does not reach the top side surface. A second pass being a second IR laser beam is directed at the bottom side having parameters selected to form a second crack line that that has a spacing relative to the embedded crack line, and the second IR laser beam causes the embedded crack line to be extended to the top side surface.

Abstract: In examples, a vehicular battery management system (BMS) comprises a set of battery cells and a secondary network node coupled to the set of battery cells. The secondary network node is configured to measure a parameter in the set of battery cells and generate a packet containing the parameter. The packet indicates a number of super frame slots that have elapsed from a start time of a super frame to the generation of the packet. The secondary network node is configured to wirelessly transmit the packet within the super frame to a primary network node. The primary network node is configured to wirelessly receive the packet and to determine a time at which the secondary network node generated the packet based on the indication, a time duration of each slot in the super frame, and the start time of the super frame.

Abstract: A controller area network including one or more first network nodes biased from a first power supply voltage, and a second network node biased from a second, lower, power supply voltage. The second network node includes a transmitter driving a differential voltage onto bus lines to communicate a dominant bus state at a second dominant state common mode voltage, a receiver coupled to the bus lines, sense circuitry to sense a common mode voltage at the bus lines, and control circuitry to control a recessive state common mode voltage in response to the sensed dominant state common mode voltage.