Abstract: A vehicle tire monitoring methodology is based on embedding into a tire at least one tire inductor coil with multiple circumferential windings. A tire condition that causes deformation of the tire, causes deformation of the tire inductor coil. A tire condition (such as pressure, speed, damage or deterioration) can be monitored by acquiring tire coil response measurements corresponding to an inductive response to the tire condition that causes deformation of the tire, and thereby deformation of the tire inductor coil, and then converting the tire coil response into data representing the tire condition. Multiple circumferential tire inductor coils can be embedded (such as into the tread and/or sidewalls), so that tire monitoring can involve acquiring respective tire coil responses corresponding to a tire condition that causes differential tire coil responses (such as steering direction), which can be converted into data representing the tire condition.

Abstract: Methods and apparatus for operating a DC-to-DC voltage converter that has a power stage that includes at least one switching transistor. The output voltage of the DC-to-DC voltage converter is monitored. If the output voltage drops below a lower output voltage threshold, a series of drive pulses is provided to the at least one switching transistor to commence switching of the at least one switching transistor. If the output voltage rises above an upper output voltage threshold, a random number of additional drive pulses is provided to the at least one switching transistor and then the provision of drive pulses to the at least one switching transistor is ceased.

Abstract: A tire pressure sensor has an RFID (radio frequency identification) device having a parallel resonant circuit including an inductor and a first capacitor for generating a first radio frequency (RF) signal for transmission to a reader circuit, and a second capacitor coupled across the parallel resonant circuit by a first switch in a first position and generating a second RF signal for transmission to the reader circuit. A capacitive pressure sensor is coupled across the parallel resonant circuit by the first switch in a second position for generating a third frequency RF signal for transmission to the reader, wherein a difference in frequency between the first and third RF signals is indicative of a pressure of a tire.

Abstract: In a switched mode inductive DCDC converter having a first mode that conducts a first current path through an inductor and through a first switch, and a second mode that conducts a second current path through the inductor and through a second switch, a detecting component detects a parameter. The detecting component outputs a biasing signal extend the turn OFF time of one of the switches in order to decrease a voltage build up on the other switch.

Abstract: An RFID transponder having an analog front end receiver having an attenuator coupled to receive an RF-signal from an antenna and to attenuate the RF-signal, an amplifier having a fixed amplifier gain and being coupled to receive and to amplify the attenuated RF-signal and a control unit coupled to control a gain of the attenuator, wherein the control unit is configured to control the attenuator gain in response to a level of the amplified RF-signal, the control unit is configured to have a plurality of predetermined states causing the attenuator to increase (step-up) or to decrease (step-down), its gain by a predefined step size, wherein the step size of a step-up is equal to or smaller than the step size of a step-down and wherein the control unit is further configured to switch, upon reaching or exceeding a predefined threshold value, from a first to a second state having a smaller step size and causing the attenuator to change the gain such that the slope of the RF signal inverts and to switch, upon reachi

Abstract: A level shifter circuit has a plurality of channels for providing signals to a capacitive load and has circuits for sharing charge stored in the capacitive load between the channels. A first pair of channel clock generating circuits are coupled respectively to a first pair of channels. A second pair of channel clock generating circuits are coupled respectively to a second pair of channels. A pair of switches couple the first pair of channels together and the second pair of channels together, respectively, for sharing charge between the channels. A single resistor is coupled in circuit with all of the channels for controlling a slope of charge sharing between channels.

Abstract: A power conversion system includes a maximum load current controller that is operable to limit a load current. For example, in a power conversion system operating in a discontinuous conduction mode (DCM), the maximum load current controller limits the load current by determining an idle period in an active cycle for power switches of the maximum load current controller. The maximum load current controller is optionally operable to approximate values for the time idle period that are substantially equal to theoretically calculated values.

Abstract: Disclosed examples include high-efficiency integrated circuits and inductive capacitive DC-DC converters with a first converter stage including first and second switches and an inductor, and a second converter stage including third and fourth switches and a flying capacitor. A dual mode control circuit regulates output voltage signal in a first mode when the output voltage signal is below a threshold by pulse width modulating the switches of the first converter stage. When the output voltage exceeds the threshold, the control circuit operates in a second mode with a first state to close the first and third switches, and a second state to close the fourth switch to connect the inductor in series with the flying capacitor. Dual mode operation of the first and second stages facilitates buck-boost operation with reduced inductor losses and converter switching losses, and the integrated circuit can be used in boost, buck or other configurations.

Abstract: A DCDC converter includes a transconductance amplifier, a comparator, a current driving component, an output impedance, a switch, a clamp resistor and a p-channel FET. The transconductance amplifier outputs a transconductance current and a switch control signal. The comparator has a two n-channel FET inputs forming a differential pair and outputs a compared signal. The current driving component generates an output current based on the compared signal. The output impedance component generates an output DC voltage based on the output current. The switch is between the two n-channel FETs and can open and close based on the switch control signal. The clamp resistor is arranged in series with the switch. The p-channel FET is in series with the clamp resistor and is controlled by the output DC voltage.

Abstract: Single inductor-multiple output (SIMO) DC-DC converter, having an output node which is coupled to one side of the single inductor to receive a load current. A plurality of output switches which are coupled to the output node for switching the load current from the output node to a plurality of output lines is provided. Each output line has a load capacitor. Further, each output line may comprise a charge pump which is coupled to the output switch and the load capacitor of the output line.

Abstract: Plaintext analysis as a countermeasure against side channel attacks. A system is disclosed that includes an encryption/decryption module performing an encryption algorithm for encrypting plaintext data using a secure encryption key stored in non-volatile memory coupled to the encryption/decryption module, the encryption/decryption module further performing an algorithm for decrypting encrypted ciphertext using the secure encryption key; and a plaintext analysis module coupled to the plaintext data, the plaintext analysis module performing an analysis and determining whether the plaintext data correlates to expected plaintext data, the plaintext analysis module outputting a signal indicating a side channel attack, responsive to the determining. Additional methods and apparatus are disclosed.

Abstract: This invention generally relates to the technical field of integrated circuits. More specifically the invention relates to output stages for providing an output signal, into which an integrated circuit may be used. An aspect relates to an integrated circuit capable of driving an external class-B output stage in a manner that allows providing a continuous output signal over the full range of desired outputs. The integrated circuit may comprise a class-AB output stage working in conjunction with the class-B output stage so as to provide a hybrid output stage. The integrated circuit may prevent dead band problems commonly faced when employing a class-B output stage. The integrated circuit may also reduce the quiescent current of the hybrid output stage. This may have further advantages, such as for example, the output stage producing less heat/power than needs to be dissipated.

Abstract: An integrated circuit (IC) for driving a light emitting semiconductor device is provided. The IC includes an input stage configured to receive a first input signal with a first differential pair of bipolar transistors and a second input signal with a second differential pair of bipolar transistors and to provide a pre-driver output signal being a superposition of the first input signal and the second input signal and an output stage including a third differential pair of bipolar transistors for receiving the pre-driver output signal of the input stage and for driving the light emitting semiconductor device in response to the pre-driver output signal, wherein the IC is configured to pre-distort the pre-driver output signal of the input stage so as to compensate a signal distortion of the output stage.

Abstract: A DC-DC converter has a high-side transistor series with a low-side transistor and an inductor connected to a node therebetween, a gate driver circuit has a high-side gate driver circuit coupled to the high-side transistor; a low-side gate driver circuit coupled to the low-side transistor; a minimum pulse with circuit coupled to one of the high-side and low-side gate, the minimum pulse width circuit adaptively controlling a pulse width of a drive signal to the high-side or low-side transistor by the propagation delay of the respective gate driver circuit.

Abstract: A level shifter circuit has a plurality of channels for providing signals to a capacitive load and has circuits for sharing charge stored in the capacitive load between the channels. A first pair of channel clock generating circuits are coupled respectively to a first pair of channels. A second pair of channel clock generating circuits are coupled respectively to a second pair of channels. A pair of switches couple the first pair of channels together and the second pair of channels together, respectively, for sharing charge between the channels. A single resistor is coupled in circuit with all of the channels for controlling a slope of charge sharing between channels.

Abstract: A light system (FIG. 2) is disclosed. The light system includes a plurality of series connected light emitting diodes (240-246). Each of a plurality of switching devices (230-236) has a control terminal and each has a current path coupled in parallel with a respective LED. A plurality of fault detector circuits (220-226) are each coupled in parallel with a respective light emitting diode. Each fault detector circuit has a first comparator (FIG. 7, 704) arranged to compare a voltage across the respective light emitting diode to a respective first reference voltage (708). When a fault is defected, a control signal is applied to the control terminal to turn on a respective switching device of the plurality of switching devices.

Abstract: An LLC converter having a bridge circuit coupled to an input voltage at least one pair of power switches, a resonant network, coupled to the bridge circuit and driven by power switches, an output transformer coupled to the resonant network having first and second primary side windings and a secondary side winding, a current sense transformer on the primary side in series to the resonant network and the first primary winding, an integrator circuit coupled in parallel to the second primary side winding and in parallel to the secondary side winding of the current sense transformer the transformer providing an output current of the LLC series resonant converter and a frequency adjustment controller coupled to at least one pair of power switches and the current sense transformer and the integrator circuit providing driving signals to the at least one pair power switches.

Abstract: An electronic device and method for half duplex data transmission in a long range keyless entry and go system, and more specifically to an RFID transponder, a corresponding read/write (R/W) unit and methods for operating the RFID transponder and the R/W-unit. There is a first coil, a second coil and a third coil, being arranged as a three-dimensional antenna, a first capacitor, a second capacitor and a third capacitor couplable in parallel to the first coil, the second coil and the third coil, respectively, for selectively forming a first, a second and a third parallel-resonant circuit for receiving radio signals, a series-resonant circuit for transmitting radio signals and a control stage configured to either use one of the first, second or third parallel-resonant circuits for receiving radio signals or the series-resonant circuit for transmitting signals.

Abstract: In a switched mode inductive DCDC converter having a first mode that conducts a first current path through an inductor and through a first switch, and a second mode that conducts a second current path through the inductor and through a second switch, a detecting component detects a parameter. The detecting component outputs a biasing signal extend the turn OFF time of one of the switches in order to decrease a voltage build up on the other switch.

Abstract: A bandgap reference (BGR) startup verification circuit includes a current minor for receiving an output current from a bandgap reference (BGR) circuit and generating output currents therefrom. A first verification sub-circuit is coupled to receive a first output current to generate a detection voltage (Vdet) and includes a voltage comparator receiving Vdet and a voltage output of the BGR circuit (VBG) to provide a first verification output. A second verification sub-circuit including a voltage comparator is coupled to receive a second output current and a second reference current and provide a second verification output. A third verification sub-circuit includes a current comparator coupled to receive a third output current and a third reference current and provide a third verification output. A digital state machine has inputs receiving the first, second and third verification output, and circuitry for processing these outputs to determine whether the BGR circuit has properly started.