Abstract: A processor includes an instruction fetch unit and an instruction decode unit. The instruction fetch unit includes an instruction pre-fetch buffer and is configured to fetch instructions from memory into the instruction pre-fetch buffer. The instruction decode unit is coupled to the instruction pre-fetch buffer and upon decoding a call instruction from the instruction pre-fetch buffer, causes next N instruction words of the instruction pre-fetch buffer to be preserved for execution after completing execution of a software module indicated by the call instruction, and causes the instruction fetch unit to begin fetching instructions of the software module from the memory at an address indicated by the call instruction. Upon completion of execution of the software module, the instruction decode unit begins to decode the preserved N instruction words while the instruction fetch unit concurrently fetches instruction words from beginning at an address after the N instruction words.

Abstract: A system on a chip (SoC) includes a transceiver comprising a transmitter having a power amplifier and a receiver having a signal buffer. At least one of the transmitter and receiver has a configurable portion that can be configured to produce a range of waveforms (both in waveshape as well as duty cycle). A low cost built in self test (BIST) logic is coupled to the transceiver. The BIST logic is operable to calibrate the configurable portion of the transceiver to produce a waveform that has a selected harmonic component that has an amplitude that is less than a threshold value. Current consumed by the transceiver may be dynamically reduced by selecting an optimized waveform that has low harmonic components.

Abstract: A DCDC converter includes a transconductance amplifier, a comparator, a current driving component, an output impedance, a switch, a clamp resistor and a p-channel FET. The transconductance amplifier outputs a transconductance current and a switch control signal. The comparator has a two n-channel FET inputs forming a differential pair and outputs a compared signal. The current driving component generates an output current based on the compared signal. The output impedance component generates an output DC voltage based on the output current. The switch is between the two n-channel FETs and can open and close based on the switch control signal. The clamp resistor is arranged in series with the switch. The p-channel FET is in series with the clamp resistor and is controlled by the output DC voltage.

Abstract: A power supply unit includes a boost converter having an input node and output node. The output node is coupled to a high-side of an H-bridge that is for supplying power to a capacitive load that is coupled to a first node and to a second node of the H-bridge. A first diode is coupled in forward direction between the first node of the H-bridge and the input node of the boost converter. A second diode is coupled in forward direction between the second node of the H-bridge and the input node of the boost converter.

Abstract: A system for providing a load current at a specific voltage to a circuit block of an integrated circuit (IC) includes a plurality of charge pumps and a control circuit to generate a control signal for each of the charge pumps. The control signal causes each of the charge pumps to be enabled, partially enabled, or disabled, and controls at least one of the charge pumps independently of the other charge pumps.

Abstract: A system and method for controlling operation of a pipeline. In one embodiment, a pipelined datapath includes a plurality of processing stages and a pipeline controller. Each of the processing stages is configured to further processing provided by a previous one of the processing stages. The pipeline controller is configured to control operation of the processing stages. The pipeline controller includes a pipelined finite state machine. The pipelined finite state machine includes a plurality of control stages. Each of the control stages is configured to control operation of a single one of the processing stages, and to receive a state value that defines a state of the control stage for controlling the single one of the processing stages from a previous control stage.

Abstract: A tire pressure sensor has an RFID (radio frequency identification) device having a parallel resonant circuit including an inductor and a first capacitor for generating a first radio frequency (RF) signal for transmission to a reader circuit, and a second capacitor coupled across the parallel resonant circuit by a first switch in a first position and generating a second RF signal for transmission to the reader circuit. A capacitive pressure sensor is coupled across the parallel resonant circuit by the first switch in a second position for generating a third frequency RF signal for transmission to the reader, wherein a difference in frequency between the first and third RF signals is indicative of a pressure of a tire.

Abstract: A system for providing a load current at a specific output voltage to a circuit block of an integrated circuit (IC) includes a supply node at a supply voltage, a charge pump, and a cross-coupling circuit. The charge pump includes a first a first capacitor to charge while a first clock signal is high and a second capacitor to charge while a second clock signal is high. Each of the capacitors has a top plate node, a bottom plate node, a ground node, and an intermediate node between the bottom plate node and the ground node. The cross-coupling circuit couples the intermediate node of the first capacitor to the supply node while the second clock signal is high and couples the intermediate node of the second capacitor to the supply node while the first clock signal is high.

Abstract: A system for providing a load current at a specific output voltage to a circuit block of an integrated circuit (IC) includes a supply node at a supply voltage, a charge pump, and a cross-coupling circuit. The charge pump includes a first a first capacitor to charge while a first clock signal is high and a second capacitor to charge while a second clock signal is high. Each of the capacitors has a top plate node, a bottom plate node, a ground node, and an intermediate node between the bottom plate node and the ground node. The cross-coupling circuit couples the intermediate node of the first capacitor to the supply node while the second clock signal is high and couples the intermediate node of the second capacitor to the supply node while the first clock signal is high.

Abstract: A system for providing a load current at a specific voltage to a circuit block of an integrated circuit (IC) includes a plurality of charge pumps and a control circuit to generate a control signal for each of the charge pumps. The control signal causes each of the charge pumps to be enabled, partially enabled, or disabled, and controls at least one of the charge pumps independently of the other charge pumps.

Abstract: A method of making an electrical assembly includes making a laminate substrate, embedding a plurality of integrated circuit dies in the laminate substrate, forming a plurality of through-holes in the laminate substrate and adding conductive material to the through-holes, and making at least one saw cut extending through the laminate substrate and through the plurality of through-holes and the conductive material therein to form at least one laminate block with a cut face and a plurality of sectioned through-holes.

Abstract: The invention relates to an electronic device and a method for DC-DC conversion using a comparator for generating an output signal for driving a power switch of a switch mode DC-DC converter. The electronic device is configured to reduce a bias current of the comparator with a first slope in response to a decreasing load and to increase the bias current of the comparator with a second slope in response to an increasing load, wherein the second slope is steeper than the first slope.

Abstract: Improved preamplifier circuits for converting single-ended input current signals to differential output voltage signals, including first and second transimpedance amplifiers with input transistors operating according to bias currents from a biasing circuit, output transistors and adjustable feedback impedances modified using an automatic gain control circuit, as well as a reference circuit controlling the bias currents according to an on-board reference current and the single-ended input or the differential output voltage signals from the transimpedance amplifiers.

Abstract: A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.

Abstract: A system and method for reducing pipeline latency. In one embodiment, a processing system includes a processing pipeline. The processing pipeline includes a plurality of processing stages. Each stage is configured to further processing provided by a previous stage. A first of the stages is configured to perform a first function in a pipeline cycle. A second of the stages is disposed downstream of the first of the stages, and is configured to perform, in a pipeline cycle, a second function that is different from the first function. The first of the stages is further configured to selectably perform the first function and the second function in a pipeline cycle, and bypass the second of the stages.

Abstract: A radio frequency identification (RFID) tag. In one embodiment, an RFID tag includes an integrated circuit die. The integrated circuit die includes circuitry configured to store information and transmit the stored information responsive to reception of a radio frequency (RF) signal. The integrated circuit die also includes an antenna coupled to the circuitry. The antenna is configured to transmit and receive RFID signals. Further, the antenna and the interconnects of the circuitry are formed of a same metal, and fabricated using a same semiconductor process.

Abstract: Compact, low power fluxgate magnetic sensor readout circuits and apparatus are presented in which demodulator or rectifier circuit to modulates a sense signal from the fluxgate sense coil, and the demodulated signal is provided to an amplifier circuit with a transconductance or other amplifier and one or more feedback capacitors connected between the amplifier input and amplifier output to integrate the amplifier output current and provide a voltage output signal indicating the magnetic field sensed by the fluxgate sensor.

Abstract: Improved magnetic sensor excitation circuitry is presented for providing a periodic bidirectional excitation waveform to a fluxgate magnetic sensor excitation coil using a bridge circuit connected to the excitation coil and having lower transistors for switched selective connection to a current mirror input transistor to mirror a current provided by pulsed current source, and with integrated filtering to control pulse rise times and slew rate.

Abstract: Hybrid magnetic current sensors and sensing apparatus are presented with closed-loop and open-loop circuitry employs first and second integrated magnetic sensors to sense a magnetic field in a magnetic core structure gap to provide high accuracy current measurement via a closed-loop magnetic circuit with the first sensor in a nominal current range as well as open-loop current measurement using the second sensor in an extended second range to accommodate over-current conditions in a host system as well as to provide redundant current sensing functionality.

Abstract: A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK1) having a first clock frequency to generate a second clock signal (CLK20) having a second clock frequency which is an integer multiple of the first clock frequency. A shift register (SH) receives the second clock signal as a data input signal, and comprises a plurality flip-flops having clock inputs coupled to receive the first clock signal (CLK1), and further coupled so that the data output of a preceding flip-flop is coupled to be the data input of a following flip-flop. The second clock signal is shifted through the shift register (SH) in response to the first clock signal (CLK1) to generate a plurality of shifted clock signals (CLK 21, . . . , CLK32) at respective data outputs of the plurality of flip-flops.