Abstract: An output stage of an operational amplifier includes a low voltage (LV) metal oxide semiconductor (MOS) device and a dynamic current limit circuit. An output current of the operational amplifier flows through the LV MOS device. The dynamic current limit circuit is configured to sense a drain voltage of the LV MOS device and increase a clamping voltage for the LV MOS device when the drain voltage of the LV MOS device is less than a threshold voltage.

Abstract: In one example, an apparatus comprises: a primary side bridge coupled between a power input and a first ground terminal, the primary side bridge having first switching terminals coupled to first capacitor terminals; and a secondary side bridge coupled between a power output and a second ground terminal, the secondary side bridge having second switching terminals coupled to second capacitor terminals.

Abstract: A method comprises receiving a signal from a piezoelectric device and receiving a measurement of a temperature of the piezoelectric device. The method further comprises reading a first parameter from a memory, in which the first parameter depends on the temperature and relates the signal to an acceleration value and reading a second parameter from the memory, in which the second parameter represents a degree of drift of the piezoelectric device at the temperature. The method further comprises determining an acceleration of the piezoelectric device based on the signal, the first parameter, and the second parameter.

Abstract: A method for luma-based chroma intra-prediction in a video encoder or a video decoder is provided that includes filtering reconstructed neighboring samples of a reconstructed down sampled luma block, computing parameters ? and ? of a linear model using the filtered, reconstructed neighboring samples of the reconstructed down sampled luma block and reconstructed neighboring samples of a corresponding chroma block, wherein the linear model is PredC[x,y]=?·RecL?[x,y]+?, wherein x and y are sample coordinates, PredC is predicted chroma samples, and RecL? is samples of the reconstructed down sampled luma block, and computing samples of a predicted chroma block from corresponding samples of the reconstructed down sampled luma block using the linear model and the parameters.

Abstract: A pulse width modulated (PWM) amplifier includes a synchronization logic circuit having a first input configured to receive a bridge control signal and having a second input configured to receive a clock signal. The synchronization logic circuit is configured to provide a slope switch signal and a reference switch signal. The PWM amplifier includes a ramp generator having a first input configured to receive a first voltage supply and having a second input configured to receive a second voltage supply and having a third input configured to receive the reference switch signal and having a fourth input configured to receive the slope switch signal. The ramp generator is configured to provide a ramp signal having a first slope responsive to the slope switch signal in a first state and having a second slope responsive to the slope switch signal in a second state and to provide the clock signal.

Abstract: A system and method for providing both localized and distributed transmission modes for EPDCCH is disclosed, where one EPDCCH comprises of one or multiple CCEs. Localized versus distributed transmission may be defined in terms of the EPDCCH to CCE resource mapping. In a localized transmission CCEs are restricted to be contained within one PRB. In a distributed transmission a CCE spans over multiple PRBs. A UE can be configured to either receive the EPDCCH only in localized or only in distributed transmissions. A UE can also be configured to expect EPDCCH transmissions in both localized and distributed transmissions. In each PRB configured by the higher layer as an EPDCCH resource, 24 REs that may be used for any DMRS transmission are always reserved and not used for EPDCCH transmission.

Abstract: An example includes a circuit including a first AND gate including a first input terminal, a second input terminal, and an output terminal, a second AND gate including a first input terminal, a second input terminal, and an output terminal, and a third AND gate including a first input terminal, a second input terminal, and an output terminal. The circuit also includes an OR gate including a first input terminal coupled to the output terminal of the first AND gate, a second input terminal coupled to the output terminal of the second AND gate, a third input terminal coupled to the output terminal of the third AND gate, and an output terminal.

Abstract: A system on an integrated circuit (IC) chip includes an input terminal and a return terminal, a heater, a thermopile, and a switch device. The heater is coupled between the input terminal and the return terminal. The thermopile is spaced apart from the heater by a galvanic isolation region. The switch device includes a control input coupled to an output of the thermopile. The switch device is coupled to at least one output terminal of the IC chip.

Abstract: In one example, a circuit comprises: a controller, an electrostatic discharge (ESD) circuit, and a driver circuit. The controller has a driver control output. The ESD circuit has a driver control input and an ESD output, the driver control input coupled to the driver control output. The driver circuit has a driver input and a driver output, the driver input coupled to the ESD output.

Abstract: One example described herein includes a light-emitting diode (LED) driver system. The system includes an error amplifier configured to compare an input voltage with a reference voltage to generate a control voltage. The system further includes an amplifier output stage configured to control an output current through a first current path and a shunt current through a second current path based on the control voltage. The amplifier output stage comprises a slew-rate controller configured to control a slew-rate of the shunt current. The shunt current can be provided through a shunt resistor in the second current path and added to the output current to provide a total current through an LED string.

Abstract: An example circuit includes a supply comparator having a supply input, a supply reference input and a supply comparator output. The supply input is coupled to a supply input terminal, and the supply reference input is configured to receive a supply reference voltage. A controller has a comparator input, a high-side output and a low-side output. The comparator input is coupled to the supply comparator output. A high-side switch having a control input. The high-side switch is coupled between the supply input and a switch output terminal, and the high-side output is coupled to the control input of the high-side switch. A low-side switch has a control input. The low-side switch is coupled between the switch output terminal and a ground terminal, and the low-side output is coupled to the control input of the low-side switch.

Abstract: A method for coding a video sequence is provided that includes encoding a portion of a picture in the video sequence in lossless coding mode, and signaling a lossless coding indicator in a compressed bit stream, wherein the lossless coding indicator corresponds to the portion of a picture and indicates whether or not the portion of the picture is losslessly coded. A method for decoding a compressed video bit stream is provided that includes determining that lossless coding mode is enabled, decoding a lossless coding indicator from the compressed video bit stream, wherein the lossless coding indicator corresponds to a portion of a picture in the compressed video bit stream and indicates whether or not the portion of the picture is losslessly coded, and decoding the portion of the picture in lossless coding mode when the lossless coding indicator indicates the portion of the picture is losslessly coded.

Abstract: A method for concurrent execution of multiple protocols using a single radio of a wireless communication device is provided that includes receiving, in a radio command scheduler, a first radio command from a first protocol stack of a plurality of protocol states executing on the wireless communication device, determining a scheduling policy for the first radio command based on a current state of each protocol stack of the plurality of protocol stacks, and scheduling the first radio command in a radio command queue for the radio based on the scheduling policy, wherein the radio command scheduler uses the radio command queue to schedule radio commands received from the plurality of protocol stacks.

Abstract: An apparatus, including processing unit (PU) cores and computer readable storage devices storing machine instructions for determining a distance between a target object and a radar sensor circuit. The PU cores receive a beat signal generated by the radar sensor circuit and compensate for a phase difference between the received beat signal and a reconstruction of the received beat signal to obtain a phase compensated beat signal. The phase compensated beat signal is then filtered to remove spurious reflections by demodulating the phase compensated beat signal using an estimated frequency of the phase compensated beat signal. The PU cores then apply a low pass filter to the demodulated phase compensated beat signal, resulting in a modified beat signal. The PU cores then determine the distance between the target object and the radar sensor circuit using the modified beat signal.

Abstract: An example includes: a substrate having a first package surface, having a second package surface opposite the first package surface, and having a die cavity with a depth extending into the first package surface; a semiconductor die having bond pads on a first die surface and having a second die surface opposite the first die surface, the semiconductor die having a die thickness, the second die surface of the semiconductor die mounted in the die cavity; a cover over a portion of the first die surface; conductors coupling the bond pads of the semiconductor die to bond fingers on the first package surface of the substrate; and dielectric material over the conductors, the bond fingers, the bond pads, at least a portion of the first semiconductor die and at least a portion of the cover, wherein the dielectric material extends above the first package surface of the substrate.

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

Abstract: A current-sensing system includes a conductor for carrying a first electrical current generating a first magnetic field. A device, spaced from the conductor by a clearance, includes a semiconductor integrated circuit die in a package. The semiconductor integrated circuit die includes at least one elongated bar of a first ferromagnetic material magnetized by the first magnetic field; a sensor comprising a first coil wrapped around the at least one elongated bar to sense the bar's magnetization; and an electronic driver creating a second electrical current flowing through a second coil wrapped around the at least one elongated bar generating a second magnetic field to compensate the at least one bar's magnetization. The package has a first outer surface free of device terminals. A discrete plate of a second ferromagnetic material is positioned in the clearance and is conformal with the first outer surface of the package.

Abstract: A bandgap reference circuit includes an amplifier, a first transistor, a second transistor, a third transistor, a first resistor, and a second resistor. The amplifier is configured to generate a bandgap voltage. The first transistor is coupled to the amplifier, and passes a first PTAT current. The second transistor is coupled to the amplifier, and passes a second PTAT current. The first resistor is coupled to the amplifier and the second transistor, and passes the second PTAT current to the second transistor. The third transistor is coupled to the amplifier, and passes a third PTAT current that bypasses the first resistor and the second transistor. The second resistor is coupled to the first transistor, the second transistor, and the third transistor, and passes the first PTAT current, the second PTAT current, and the third PTAT current.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template specifies loop count and loop dimension for each nested loop. A format definition field in the stream template specifies the number of loops and the stream template bits devoted to the loop counts and loop dimensions. This permits the same bits of the stream template to be interpreted differently enabling trade off between the number of loops supported and the size of the loop counts and loop dimensions.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.