Abstract: A method of manufacturing an integrated circuit includes forming first and second false collector regions of a first conductivity type adjacent to a surface of an epitaxial layer of semiconductor material. The first false collector region is located laterally on a first side of a base region. The base region is formed within the epitaxial layer and has a second conductivity type. The second false collector region is located laterally on a second side of the base region. The second side is opposite the first side of the base region. The base region is a base of a parasitic bipolar junction in an isolation region of an active semiconductor device.

Abstract: A semiconductor device has a deep trench in a semiconductor substrate of the semiconductor device, with linear trench segments extending to a trench intersection. Adjacent linear trench segments are connected by connector trench segments that surround a substrate pillar in the trench intersection. Each connector trench segment has a width at least as great as widths of the linear trench segments connected by the connector trench segment. The deep trench includes a trench filler material. The deep trench may have three linear trench segments extending to the trench intersection, connected by three connector trench segments, or may have four linear trench segments extending to the trench intersection, connected by four connector trench segments.

Abstract: A modulation device may include a variable burst regulator and a current-driven clock generator. The modulation device may include a first output terminal configured to provide a modulated voltage for an operating frequency over a modulation period. The current-driven clock generator may include a second input terminal configured to receive a buffered version of the modulated voltage. The current-driven clock generator may include a second output terminal configured to provide a modulated current during the modulation period. The operating frequency may be proportional to the modulated current. The operating frequency may control the operating frequency over the modulation period.

Abstract: A method for calibrating analog-to-digital conversion includes converting, by an analog-to-digital converter (ADC), a first input voltage to a first digital code. The first input voltage is generated from a reference voltage used as a reference voltage by the ADC. The method includes converting, by the ADC, a second input voltage to a second digital code. The second input voltage is generated from the reference voltage used as the reference voltage by the ADC. The method also includes calculating a calibration factor based on the first digital code, the second digital code, the first input voltage, and the second input voltage, converting, by the ADC, a third voltage to a third digital code, and correcting the third digital code using the calibration factor.

Abstract: An integrated circuit comprises a set of processor cores, wherein each processor core of the set of processor cores includes BIST logic circuitry and multiple memory blocks coupled to the BIST logic circuitry. Each processor core further includes multiple power control circuitry, where each power control circuitry of the multiple power control circuitry is coupled to a respective processor core of the set of processor cores, multiple isolation circuitry, where each isolation circuitry of the multiple isolation circuitry is coupled to a respective processor core of the set of processor cores, a built-in-self repair (BISR) controller coupled to the each of the set of processor cores, each of the multiple power control circuitry, and each of the multiple isolation circuitry, and a safety controller coupled to the BISR controller, the multiple power control circuitry, and to the multiple isolation circuitry.

Abstract: An integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.

Abstract: An optical distance measuring system includes a first transmitter, a first solid state device, and a receiver. The first transmitter is configured to generate a first optical waveform. The first solid state device is configured to receive the first optical waveform and steer the first optical waveform toward a target object. The receiver is configured to receive the first optical waveform reflected off of the first target object and determine a distance to the first target object based on a time of flight from the transmitter to the first target object and back to the receiver.

Abstract: An example apparatus includes: a pullup circuit coupled to a first USB terminal; a first pulldown circuit coupled to the first USB terminal; a second pulldown circuit coupled to a second USB terminal; a third pulldown circuit coupled to a third USB terminal; a fourth pulldown circuit coupled to a fourth USB terminal; a high-speed termination detection circuit including: a current source including a first supply terminal and a second supply terminal, the first supply terminal coupled to the first USB terminal, the second supply terminal coupled to the second USB terminal; a first comparator including a first comparator terminal and a second comparator terminal, the first comparator terminal coupled to the first USB terminal; and a second comparator including a third comparator terminal and a fourth comparator terminal, the third comparator terminal coupled to the second USB terminal; and a controller including a first control terminal and a second control terminal, the first control terminal coupled to the sec

Abstract: Methods, apparatus, systems and articles of manufacture to facilitate atomic compare and swap in cache for a coherent level 1 data cache system are disclosed. An example system includes a cache storage; a cache controller coupled to the cache storage wherein the cache controller is operable to: receive a memory operation that specifies a key, a memory address, and a first set of data; retrieve a second set of data corresponding to the memory address; compare the second set of data to the key; based on the second set of data corresponding to the key, cause the first set of data to be stored at the memory address; and based on the second set of data not corresponding to the key, complete the memory operation without causing the first set of data to be stored at the memory address.

Abstract: A microelectronic device includes a hybrid component. The microelectronic device has a substrate including silicon semiconductor material. The hybrid component includes a silicon portion in the silicon, and a wide bandgap (WBG) structure on the silicon. The WBG structure includes a WBG semiconductor material having a bandgap energy greater than a bandgap energy of the silicon. The hybrid component has a first current terminal on the silicon, and a second current terminal on the WBG semiconductor structure. The microelectronic device may be formed by forming the silicon portion of the hybrid component in the silicon, and subsequently forming the WBG structure on the silicon.

Abstract: Several methods and systems for chroma residual data prediction for encoding blocks corresponding to video data are disclosed. In an embodiment, at least one coefficient correlating reconstructed luma residual samples and corresponding reconstructed chroma residual samples is computed for one or more encoded blocks of video data. Predicted chroma residual samples are generated for encoding a block of video data based on corresponding reconstructed luma residual samples and the at least one coefficient.

Abstract: Various systems and circuits are provided. One such system includes input interfaces to receive items of input data of different types; output interfaces, each of a different type; an interconnect coupled to the input interfaces and to the output interfaces; and an multichip hub that includes buffers respectively corresponding to the types of input data, context memory blocks, and a data movement engine with a context mapper to determine a context of each item of input data received and provide the item of input data to a corresponding context memory block. Multiple processing blocks within the multichip hub are each configured to perform a respective processing operation. The data movement engine receives context configuration data to determine, for each item of input data received, which of the multiple processing operations are to be applied to the item of input data.

Abstract: A method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof, wherein each non-consecutive data elements of a register is retrieved to be stored to interleave with each non-consecutive data elements of a different register upon an executive of an interleaving store instruction, wherein a mask instruction directing a lane of a storage space in which the non-consecutive data elements are stored is executed in conjunction with the interleaving store instruction, and wherein a processor of a second type is configured to emulate a processor of a first type to store the non-consecutive data elements the same as non-consecutive data elements stored in the first type processor.

Abstract: In some examples, a method includes determining, during a boot sequence of a controller, a hash value for data of a block of a flash storage device, the block including executable code, determining a bit pattern based on a randomly generated number, extracting a subset of data bits of the hash value according to the bit pattern to obtain a snippet, and storing the snippet to a secure storage device.

Abstract: A converter includes a transformer having a primary and secondary windings. The primary winding has first and second winding terminals. A switch network has first-sixth switch network terminals. The first switch network terminal couples to the first winding terminal. The second switch network terminal couples to the second winding terminal. A first transistor has a first control input and first and second current terminals. The second current terminal couples to the third switch network terminal. A second transistor has a second control input and third and fourth current terminals. The fourth current terminal couples to the fourth switch network terminal. A third transistor has a third control input and fifth and sixth current terminals. The fifth current terminal couples to the fifth switch network terminal. A fourth transistor has a fourth control input and seventh and eighth current terminals. The seventh current terminal couples to the sixth switch network terminal.

Abstract: In an example, a method includes communicating between a first BLUETOOTH device and a second BLUETOOTH device via a first channel within a channel set at a first connection event using first channel specific parameters. The method also includes determining, by the first BLUETOOTH device, one or more channel cluster operation parameters for a second channel within the channel set at a second connection event using second channel specific parameters. The method includes communicating over the second channel during the second connection event from the first BLUETOOTH device to the second BLUETOOTH device using renegotiated second channel specific parameters.

Abstract: In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

Abstract: A gate driver circuit includes first through third transistors, a first voltage clamp, and control logic. The first transistor has a first control input and first and second current terminals. The first current terminal couples to a first voltage terminal. The first voltage clamp couples between the first voltage terminal and the first control input. The second transistor couples between the first control input and the second voltage terminal. The third transistor couples between the first control input and the second voltage terminal. The third transistor is smaller than the second transistor. The control logic is configured to turn on both the second and third transistors to thereby turn on the first transistor, and the first control logic configured to turn off the second transistor after the first transistor turns on while maintaining in an on-state the third transistor to maintain the first transistor in the on-state.

Abstract: In an example, a system includes a differential amplifier having a first input terminal and a second input terminal, the differential amplifier configured to be coupled to a boost diode of a boost converter. The system also includes an input diode coupled to the first input terminal and the second input terminal. The system includes a pull-up circuit coupled to the input diode and configured to be coupled to the boost diode. The system also includes a pull-down circuit coupled to the pull-up circuit. The system includes a transistor coupled to the pull-up circuit and the pull-down circuit.

Abstract: A method for time multiplexing subframes on a serving cell to a user equipment, wherein one set of subframes operate with the legacy LTE transmission format and one set of subframes operate with an evolved transmission format comprising reduced density CRS transmission without a PDCCH control region.