Abstract: An integrated circuit (IC) includes a tristatable output buffer having a control input. The IC includes an input buffer having a buffer output. The IC further includes a delay circuit having a delay circuit input, a first delay circuit output, and a second delay circuit output. The delay circuit input is coupled to the buffer output. The IC also includes a tristate circuit coupled to the first delay circuit output and to the second delay circuit output. The tristate circuit having a tristate circuit output coupled to the control input.

Abstract: A circuit includes a resonator, a transistor pair, and a common-mode feedback circuit. The transistor pair is cross-coupled across the resonator. The common-mode feedback circuit is coupled to the transistor pair. The common-mode feedback circuit includes first and second degeneration cells. The second degeneration cell is connected in parallel with the first degeneration cell. The second degeneration cell is configured to switchably vary a current flow through the transistor pair.

Abstract: An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of the bias value generator circuit (3900) and further responsive to a second instruction having an operand to repeatedly issue the second instruction with the operand varied in an operand value range determined as a function of the varying bias value.

Abstract: A method for automatic generation of calibration parameters for a surround view (SV) camera system is provided that includes capturing a video stream from each camera comprised in the SV camera system, wherein each video stream captures two calibration charts in a field of view of the camera generating the video stream; displaying the video streams in a calibration screen on a display device coupled to the SV camera system, wherein a bounding box is overlaid on each calibration chart, detecting feature points of the calibration charts, displaying the video streams in the calibration screen with the bounding box overlaid on each calibration chart and detected features points overlaid on respective calibration charts, computing calibration parameters based on the feature points and platform dependent parameters comprising data regarding size and placement of the calibration charts, and storing the calibration parameters in the SV camera system.

Abstract: Described examples include an integrated circuit includes a protected node and a first transistor having a source coupled to the protected node, a gate and a drain coupled to a ground, wherein the first transistor is a MOSFET transistor. The integrated circuit also includes a second transistor having a first current handling terminal coupled to the protected node, a second current handling terminal coupled to the ground and a control terminal coupled to a reference potential, where the second transistor is configured to be off when a first voltage on the control terminal of the second transistor is less than a second voltage on the first current handling terminal of the second transistor.

Abstract: In some examples, a semiconductor device comprises a substrate, a trench, and a layer of a dielectric material. The substrate includes a semiconductor material and has opposing first and second surfaces. The trench extends between the first surface and the second surface, the trench having the dielectric material. The layer of the dielectric material is on the second surface of the substrate and is contiguous with the dielectric material in the trench.

Abstract: In one example, an apparatus comprises a substrate, a first piezoelectric flap, and a second piezoelectric flap. The substrate has an opening. The first piezoelectric flap has a first end on the substrate and has a first portion extending over a first part of the opening, the first piezoelectric flap including first electrodes, in which the first electrodes extend no more than half of a first length of the first portion. The second piezoelectric flap has a second end on the substrate and has a second portion extending over a second part of the opening, the second piezoelectric flap including second electrodes, in which the second electrodes extend no more than half of a second length of the second portion.

Abstract: In some examples, an apparatus comprises a chopper, a first microelectromechanical system (MEMS) device, a second MEMS device, and a processing circuit. The chopper configured is to repeatedly switch states to enable and disable provision of a light signal. The first MEMS device is configured to provide first and second irradiance signals when the chopper is in, respectively, first and second states The second MEMS device is configured to provide first and second reference signals when the chopper is in, respectively, the first and second states. The processing circuit is configured to generate a first signal based on the first irradiance signal and the first reference signal, generate a second signal based on the second irradiance signal and the second reference signal, and provide a third signal at the processing output representing an irradiance measurement of the light source based on a difference between the first and second signals.

Abstract: Described examples include an integrated circuit having a transistor with a first gate on a first gate insulating layer. The transistor also has second gate separated from the first gate by a gate gap. The integrated circuit also includes a channel well at the gate gap extending under the first gate and the second gate. The transistor has a first source in the channel adjacent to an edge of the first gate. The transistor having a second source formed in the channel adjacent to an edge of the second gate separated from the first source by a channel gap. The transistor has at least one back-gate contact, the at least one back-gate contact separated from the first gate by a first back-gate contact gap and separated from the second gate by a second back-gate contact gap.

Abstract: A digital data processor includes an instruction memory storing instructions specifying a data processing operation and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to perform a table write in response to a look up table initialization instruction by duplicating at least one data element from a source data register to create duplicated data elements, and writing the duplicated data elements to a specified location in a specified number of at least one table and a corresponding location in at least one other table.

Abstract: An example apparatus includes: bandwidth estimator circuitry configured to: obtain a first memory transaction; and determine a consumed bandwidth associated with the memory transaction; and gate circuitry configured to: permit transmission of the memory transaction to a memory controller circuitry; determine whether to gate a second memory transaction generated by a source of the first memory transaction based on the consumed bandwidth of the first memory transaction; and when it is determined to gate the second memory transaction, prevent transmission of the second memory transaction for an amount of time based on the consumed bandwidth.

Abstract: In an example, a method includes storing code for a first central processing unit (CPU) executing a first application in a first region of a memory, and storing code for a second CPU executing a second application in a second region of the memory. The method includes storing shared code for the first CPU and the second CPU in a third region of the memory. The method includes storing read-write data for the first CPU in a fourth region of the memory and storing read-write data for the second CPU in a fifth region of the memory. The method includes translating a first address from a first unique address space for the first CPU to a shared address space in the third region, and translating a second address from a second unique address space for the second CPU to the shared address space in the third region.

Abstract: In an example, a system includes a phase frequency detector (PFD) coupled to a charge pump, and a loop filter coupled to the charge pump. The system also includes a voltage controlled oscillator (VCO) coupled to the loop filter. The system includes a fast Fourier transform (FFT) engine coupled to an output of the VCO, the FFT engine configured to estimate a phase and a magnitude of reference spurs of an input reference signal. The system includes spur correction circuitry coupled to an input of the VCO, the spur correction circuitry configured to correct for the reference spurs of the input reference signal based at least in part on the phase and magnitude of the reference spurs.

Abstract: Disclosed herein are improvements to pixel pattern conversion, upsampling, and IR decontamination processes. An example includes an image processing pipeline comprising an upstream component, a pattern conversion component downstream with respect to the upstream component in the image processing pipeline, and a downstream component relative to the pattern conversion component. The pattern conversion component is configured to obtain RGB-IR pixel data produced by the upstream component of the image processing pipeline and convert the RGB-IR pixel data into RGB pixel data and IR pixel data using a conversion engine. The conversion engine is configured to demosaic the RGB-IR pixel into the RGB pixel data and the IR pixel data, remosaic the RGB pixel data into an RGB pattern and the IR pixel data into an IR pattern and remove IR contamination from the RGB pixel data of the RGB pattern for use by the downstream component.

Abstract: Various embodiments of the present technology relate to using neural networks to detect objects in images. More specifically, some embodiments relate to the reduction of computational analysis regarding object detection via neural networks. In an embodiment, a method of performing object detection is provided. The method comprises determining, via a convolution neural network, at least a classification of an image, wherein the classification corresponds to an object in the image and comprises location vectors corresponding to pixels of the image. The method also comprises, for at least a location vector of the location vectors, obtaining a confidence level, wherein the confidence level represents a probability of the object being present at the location vector, and calculating an upper-bound score based at least on the confidence level.

Abstract: A monitoring circuit for a photovoltaic module includes a measurement conditioning circuit, a microcontroller circuit, and a transmitter circuit. The measurement conditioning circuit includes a voltage sense terminal, a voltage reference terminal, and a digital measurement data output. The microcontroller circuit includes a digital measurement data input coupled with the digital measurement data output, a modulation clock input, a measurement data stream output, and a transmit select output. The transmitter circuit includes a measurement data stream input coupled with the measurement data stream output, a modulation clock output coupled with the modulation clock input, a transmit select input coupled with the transmit select output, and positive and negative output communication terminals.

Abstract: A balun includes a first winding which has a first terminal coupled to an input, and a second terminal coupled to a reference potential terminal. The balun includes a second winding magnetically coupled to the first winding. The second winding has a first terminal coupled to a first differential output, a second terminal coupled to a second differential output, and a tap coupled to the reference potential terminal. The balun includes a first capacitor which has a first terminal coupled to the first winding and a second terminal coupled to the second winding. The balun includes a third winding which has a first terminal coupled to the reference potential terminal and a floating second terminal. The balun includes a second capacitor which has a first terminal coupled to the third winding and a second terminal coupled to the second winding.

Abstract: In examples, an apparatus has input and output terminals, and includes a first transistor having a first gate, source, and drain, wherein the first source is coupled to the input terminal, and the first drain is coupled to the output terminal, a second transistor having a second gate, source, and drain, wherein the second gate is coupled to a ground terminal, and the second source is coupled to the first gate, a third transistor having a third gate, source, and drain, wherein the third gate is coupled to an enable terminal, the third source is coupled to the ground terminal, and the third drain is coupled to the second drain, and a fourth transistor having a fourth gate, source, and drain, wherein the fourth gate is coupled to the second drain, the fourth source is coupled to the second source, and the fourth drain is coupled to the input terminal.

Abstract: A method of forming a composite material includes photo-initiating a polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice. Unpolymerized monomer is removed from the polymer microlattice. The polymer microlattice is coated with a metal. The metal-coated polymer microlattice is dispersed in a polymer matrix.

Abstract: A pulse width modulator circuit with circuitry for providing a first and second pulse width modulation signal with dead time periods between the first and second pulse width modulation signals, an input for receiving a signal representative of a current in a load adapted to be driven in response to the first and second pulse width modulation signals, and circuitry coupled to the input for adjusting the dead time periods in response to the signal representative of a current.