Abstract: According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the annealing the source and the drain, a heavy ion in the source region and the drain region, depositing a nickel layer in each of the source and drain regions, and heating the substrate to form a nickel silicide region in each of the source and drain regions by heating the substrate.

Abstract: A digital controller for a power factor correction (PFC) circuit, has first means for generating a first control signal for a switching transistor to avoid continuous oscillation between an inductor and parasitic capacitance of the switching transistor during discontinuous mode operation when an input voltage is less than substantially 50% of an output voltage. Second means generates a second control signal for a switching transistor to avoid continuous oscillation between an inductor and parasitic capacitance of the switching transistor during discontinuous mode operation when an input voltage is greater than substantially 50% of an output voltage. A power factor correction circuit and a method of operating a power factor correction circuit are also disclosed.

Abstract: Example embodiments of the systems and methods of dynamic spur mitigation for wireless receivers disclosed herein comprise one or more of a detection module for detecting the presence of a spur and a determination of its frequency, a complex notch filter chain, and a frequency locked loop which ensures that the input spur is notch filtered even if it drifts after detection. When a spur is detected, the frequency of the tone is determined. The spur is then filtered, for example using a phase rotator and a DC separator. The phase rotation is removed in a subsequent stage. The non-DC component from the DC separator is used to track the spur to compensate for any shifting or drifting in the spur.

Abstract: A data storage system for detecting a location of a head relative to a magnetic media is described. This system comprises arms, a preamplifier circuit coupled to the arms for controlling the arms, a proximity sensing system positioned within the preamplifier circuit, the proximity sensing system comprising: an input stage for transmitting an input sense signal; a programmable gain stage coupled to receive the input sense signal and operative for transmitting a gain signal in response to receiving the input sense signal; a multiplexer coupled to receive the gain signal and at least one control signal, the multiplexer operative for transmitting a multiplexed signal; a detector coupled to receive the multiplexed signal and a second control signal, the detector operative for transmitting an output signal; wherein an amplitude associated with the output signal enables detecting the location of the head.

Abstract: Asynchronous sample rate conversion for use in a digital audio receiver is disclosed. Different algorithms are applied for the upsampling and downsampling cases. In the upsampling case, the input signal is upsampled and filtered, before the application of a finite impulse response (FIR) filter. In the downsampling case, the input signal is filtered by an FIR filter, and then filtered and downsampled. The FIR coefficients of the fractional delay FIR filter are calculated by evaluation of polynomial expressions over intervals of the filter impulse response, at times corresponding to the input sample points.

Abstract: A capacitance measurement system precharges first terminals (21-0 . . . 21-k . . . 21-n) of a plurality of capacitors (25-0 . . . 25-k . . . 25), respectively, of a CDAC (capacitor digital-to-analog converter) (23) included in a SAR (successive approximation register) converter (17) to a first voltage (VDD) and pre-charges a first terminal (3-j) of a capacitor (CSENj) to a second voltage (GND). The first terminals are coupled to the first terminal of the capacitor to redistribute charges therebetween so as to generate a first voltage on the first terminals and the first terminal of the capacitor, the first voltage being representative of a capacitance of the first capacitor (CSENj). A SAR converter converts the first voltage to a digital representation (DATA) of the capacitor. The capacitance can be a touch screen capacitance.

Abstract: An antenna is provided. This antenna is contained within a package that is secured to an IC (which allows radiation to propagated away for a printed circuit board so as to reduce interference), and this antenna includes two loop antennas that are shorted to ground and that “overlap” and includes a “via wall.” With this configuration, circular polarization can be achieved by varying the relative phases of the input signals, and the “via wall” improves efficiency by reducing surface waves.

Abstract: A method for generating a signal is provided. A control signal is generated in response to a comparison between a reference signal and a feedback signal. Then, charge is provided to first and second low pass filters (LPFs). The first and second LPFs have first and second bandwidths, respectively, and the second bandwidth is greater than the first bandwidth. First and second gains are then applied to the outputs from the first and second LPFs, respectively, so as to generate first and second voltages, respectively. The first gain is also greater than the second gain. The feedback signal is then generated from the sum of the first and second voltages.

Abstract: Methods for fabricating a packaged semiconductor device includes providing a metal plate having a single flat first surface and a parallel second surface. The flat first surface ending in four sawed plate sides. The plate having on the second surface at least one mesa of the same metal and a linear array of insular mesas. The at least one mesa is raised from the second surface. A single terminal of a semiconductor chip is attached to the second plate surface.

Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.

Abstract: A computer system is provided that can realize polling without increasing the processing burden on the processor. Data is read by a polling unit during a prescribed period from a prescribed address in the address space. Then, if the read data satisfies a prescribed condition, an interrupt signal is generated in the polling unit. Since processor can receive the interrupt from hardware instead of performing polling with firmware, the processing burden on processor 10 can be significantly reduced.

Abstract: In many applications, which use amplifiers that operate at less than 50% duty cycle, it would be advantageous to reduce the number amplifiers to reduce power consumption. Here, an amplifier is provided which is time multiplexed to accommodate multiple data paths. Additionally, reset circuitry or a reset mechanism is provided at the output terminals of this amplifier to briefly short the output terminals to generally prevent glitching that may result from switching between data paths.

Abstract: A loop antenna is provided. The apparatus comprises a substrate, a first metallization layer, and a second metallization layer. The substrate has first and second feed terminals and a ground terminal. The first metallization layer is disposed over the substrate and includes a first window conductive region, a first conductive region, a second conductive region, and a third conductive region. The first conductive region is disposed over and is in electrical contact with the first feed terminal; it is also is substantially circular and located within the first window region. The second conductive region is disposed over and is in electrical contact with the second feed terminal; it is also substantially circular and is located within the first window region. The a third conductive region is disposed over and is in electrical contact with the ground terminal, and the third conductive region substantially surrounds the first window region.

Abstract: Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.

Abstract: The disclosed systems and methods emphasize driving LEDs in series and in parallel with the same LED driver chip and a single inductor. For creating overlap, the systems and methods of LED color overlap disclosed herein take advantage of the fact that green and blue LEDs have the same voltage. Thus, green and blue LEDs can be driven in parallel as needed. LED suppliers can screen parts for sufficiently close voltage matching between green and blue LEDs. This is especially true when using green LED die based on a blue die with a green phosphor. Cyan may be produced by driving a green LED and a blue LED in parallel. White may produced by driving a green LED and a blue LED in parallel and a red LED in series with this green and blue parallel pair.

Abstract: For protecting a speaker, an input signal is received and filtered into component signals. A sum of the component signals is approximately equal to the input signal. The component signals include at least first and second component signals. A perceived loudness to a human from the speaker is more sensitive to the first component signal than to the second component signal. A temperature of the speaker is estimated. In response to the estimated temperature, the second component signal is scaled. An output signal is output to the speaker in response to the first component signal and the scaled second component signal.

Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.

Abstract: An imaging device is provided, comprising: a decorrelation circuit configured to receive K initial imaging signals and to perform a decorrelation operation on K initial imaging signals, respectively, to generate K decorrelated imaging signals; Kh wavelet decomposition circuits configured to perform K wavelet decomposition operations on the K decorrelated imaging signals, respectively, to generate K decomposed imaging signals; K quantization circuits configured to perform K quantization operations on the K decomposed imaging signals, respectively, to generate K quantized imaging signals; and a bit multiplexer configured to generate a compressed bit stream based on the K quantized imaging signals; a data line configured to pass the compressed bit stream; and a decompressor module configured to convert the compressed bit stream into K recovered imaging signals corresponding to the K initial imaging signals, wherein K is an integer greater than 1.

Abstract: A packaged semiconductor device has a metal plate (1200) with sawed sides (1200c), a flat first surface (1200a) and a parallel second surface (1200b); the plate is separated into a first section (1201) and a second section (1202) spaced apart by a gap (1230). The plate has on the second surface (1200b) at least one insular mesa (1205) of the same metal in each section, the mesas raised from the second plate surface. The device further has an insulating member (1231), which adheres to the first plate surface, bridges the gap, and thus couples the first and second sections together. The device further has a vertical stack (1270) of two power FET chips (1210) and (1220), each having a pair of terminals on the first chip surface (1211 and 1212; 1221 and 1222 respectively) and a single terminal on the second chip surface. The single terminals of chip (1210) and chip (1220) are attached to each other to form the common terminal (1240).

Abstract: A method for driving a brushless direct current (DC) motor is provided. The brushless DC motor has a first phase that is coupled between a first terminal and a common node, a second phase that is coupled between a second terminal and the common node, and a third phase that is coupled between a third terminal and the common node. The first and second phases are coupled to a first supply rail and a second supply rail, respectively, such that the brushless DC motor is in a first commutation state. The first phase is then decoupled from the first supply rail so as to allow first terminal to float during a window period. A first voltage difference between the first terminal and the second terminal is compared to a second voltage difference between the third terminal and the second terminal during the window period, and the brushless DC motor is commuted to a second commutation state if the first voltage difference is approximately equal to the second voltage difference.