Abstract: Circuits and methods for sampling differential input signals having wide input swings including voltages below ground potential, and capable of operating on a single positive supply voltage are disclosed. In an embodiment, the circuit includes a first input switch circuit and a second input switch circuit, a sample and hold circuitry and an operational amplifier. Each of the first and second input switch circuits includes serially connected PMOS switch and NMOS switch for receiving a differential input signal. The sample and hold circuitry includes a first sampling capacitor, a second sampling capacitor and a plurality of switches. The switches are configured to provide the differential input signal to the sampling capacitors for the sampling in a sample phase, and are configured to provide the sampled differential input signal at an output of the operational amplifier in a hold phase.

Abstract: A method is provided. A first voltage is applied to a first set of column electrodes within a touch panel during a first interval, and a second voltage is applied to a second set of column electrodes within the touch panel during the first interval. The first and second sets of electrodes are adjacent to one another, and the second voltage has the opposite polarity of the first voltage. During the first interval, a first measurement signal is received from a set of row electrodes in the touch panel, and the first measurement signal is integrated to generate a first integrated signal. The first voltage is applied to the second set of column electrodes within the touch panel during a second interval, and the second voltage is applied to the first set of column electrodes within the touch panel during the second interval.

Abstract: A method for driving a motor having a plurality of phases is provided. Initially, first, second, and third intervals for a pulse width modulation (PWM) period from first and second voltage commands are generated. The first and second voltage commands correspond to a voltage vector for the motor, and the voltage vector has an associated sector. A conversion formula is then determined for the first, second, third intervals based on the associated sector for the voltage vector. Using the conversion formula and the first, second, and third intervals, fourth, fifth, and sixth intervals are generated, and a set of PWM signals for the PWM period is generated from the fourth, fifth, and sixth intervals. The motor is then driven with the second set of PWM signals, and a current traversing the plurality of phases with a single shunt is measured.

Abstract: To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths.

Abstract: For high speed amplifiers, the parasitic capacitances between a differential input pairs and a cascoded bias network can introduce a pole that can affect performance. Here, a feedforward network has been provided that compensates for this pole by introducing a zero that effectively cancels the pole, moving the next parasitic without any additional power. This is generally accomplished by using a pair of feedforward capacitors coupled across the transistors of the cascoded bias network, which reduced power consumption.

Abstract: A method for measuring for generating a touch capacitance measurement is provided. Gain and offset control signals are generated, where the gain and offset control signals are adjusted to compensate for base capacitance of a touch sensor. The gain control signal is applied to a touch sensor during a first phase of a clock signal, and the offset control signal is applied to an output circuit during a second phase of the clock signal. The output circuit is coupled to the touch sensor during the second phase of the clock signal. The touch capacitance measurement is generated by compensating for the base capacitance with the gain and offset control signals, and a gain is applied to the touch capacitance measurement.

Abstract: A GNSS receiver includes at least one buffer and at least one correlator block. The at least one buffer stores a plurality of samples corresponding to a received signal. The at least one correlator block includes a Doppler derotation block configured to perform Doppler derotation corresponding to at least one Doppler frequency on the plurality of samples, a register array configured to be loaded with the plurality of samples on Doppler derotation corresponding to a Doppler frequency of the at least one Doppler frequency, and a correlator engine configured to generate correlation results by correlating the plurality of samples in the register array with a plurality of code phases for at least one GNSS satellite. A presence of at least one GNSS satellite signal may be detected based on coherent accumulation and a non-coherent accumulation of the correlation results.

Abstract: Display systems and methods for mobile devices and mobile devices are disclosed. In one embodiment, a display system for a mobile device is provided. The mobile device is handheld and includes a primary display screen. The display system includes an auxiliary screen and a connecting device coupled to the auxiliary screen and attachable to the mobile device. An image from the mobile device is producible on the auxiliary screen. The display system is removable from the mobile device.

Abstract: Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.

Abstract: A method and structure for a dual heat dissipating semiconductor device. A method includes attaching a drain region on a first side of a die, such as a power metal oxide semiconductor field effect transistor (MOSFET) to a first leadframe subassembly. A source region and a gate region on a second side of the die are attached to a second leadframe subassembly. The first leadframe subassembly is attached to a third leadframe subassembly, then the device is encapsulated or otherwise packaged. An exposed portion of the first leadframe subassembly provides an external heat sink for the drain region, and the second leadframe subassembly provides external heat sinks for the source region and the gate region, as well as output leads for the gate region. The third leadframe subassembly provides output leads for the drain region.

Abstract: An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.

Abstract: A process of integrated circuit manufacturing includes providing (32, 33) a spacer on a gate stack to provide a horizontal offset over the channel region for otherwise-direct application (34) of a PLDD implant dose in semiconductor, additionally depositing (35) a seal substance to provide a screen thickness vertically while thereby augmenting the spacer on the gate stack to provide an increased offset horizontally from the gate stack and form a horizontal screen free of etch, and subsequently providing (36) an NLDD implant dose for NLDD formation. Various integrated circuit structures, devices, and other processes of manufacture, and processes of testing are also disclosed.

Abstract: A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.

Abstract: An apparatus and system are provided for crest factor reduction (CFR). Preferably, a peak from the wideband signal is detected. A gain from the magnitude of the peak and a threshold can then be calculated. Based on this information, each carrier's contribution to the peak can be approximated, and a cancellation pulse coefficient for each carrier from its contribution to the peak can be calculated. A base cancellation pulse can be calculated from the cancellation pulse coefficients for each carrier, and a cancellation pulse can be calculated from the base cancellation pulse and the gain, which can then be applied to the wideband signal.

Abstract: A method of selecting an intermediate frequency (fIF) is disclosed (FIG. 7). The method includes measuring a first signal quality (704) on a first channel at a first intermediate frequency. The method further includes measuring a second signal quality (706) on the first channel at a second intermediate frequency. The intermediate frequency with the best signal quality is selected (710).

Abstract: An apparatus and method are provided. Generally, an input signal is applied across a main path (through an input network) and across a cancellation path (through a cancellation circuit). The cancellation circuit subtracts a cancellation current from the main path as part of the control mechanism, where the magnitude of the cancellation current is based on a gain control signal (that has been linearized to follow a control voltage).

Abstract: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.

Abstract: A computer implemented method selects K extreme elements of a list of N elements by partitioning each of the N elements into a plurality of sections. For each section from a most significant section to a least significant section the method selects a threshold selection determining at least K extreme entries from the list. This iteratively compares a corresponding section to a section threshold, counts a number of sections which are more extreme than the section threshold, increasing (or decreasing) the section threshold if the count is greater than K and decreasing the section threshold if the count is less than K. After finding the section threshold for the corresponding section the method forms a combined threshold by concatenation of said section thresholds in order from a most significant section to a least significant section, compares each of the N elements to the combined threshold, and selects at least K elements from the set of N elements more extreme than the combined threshold.

Abstract: Various techniques for connection setup for Bluetooth Low Energy (BLE) devices are disclosed. The various embodiments save power. In one example, an apparatus (such as a BLE slave) includes a controller configured to transmit advertising packets and, based on responses to the packets, and lack thereof, the controller estimates the length of the scan window and scan interval. In another embodiment, an apparatus such as a master device is configured to generate a scan update packet that specifies the scan window length, scan interval, and start and end times for that master. The controller is configured to transmit the packet to one or more slave devices.

Abstract: A DC-DC converter, having an input voltage and an output voltage, includes an inductor and a switch switching the input voltage to an input side of the inductor, where a feedback path controlling initiation of closing the switch includes capacitive coupling of the voltage at the input side of the inductor.