Abstract: A multi-chip isolation (ISO) device package includes a leadframe including leads, an interposer substrate including a top copper layer and a bottom metal layer, with a dielectric layer in-between. A first IC die and a second IC die include circuitry including a transmitter or a receiver, and first and second bond pads are both attached top side up in the package. A laminate transformer is attached to the top copper layer positioned lateral to the IC die. Bondwires wirebond the first bond pads to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to a second group of the leads or the lead terminals. A mold compound provides encapsulation.

Abstract: A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.

Abstract: A method for encoding video data is provided that includes determining whether or not a parent coding unit of a coding unit of the video data was predicted in intra-prediction block copy (IntraBC) mode and, when it is determined that the parent coding unit was not predicted in IntraBC mode: computing activity of the coding unit, determining an IntraBC coding cost of the coding unit by computing the IntraBC coding cost of the coding unit using a two dimensional (2D) search when the activity of the coding unit is not than an activity threshold, and computing the IntraBC coding cost of the coding unit using a one dimensional (1D) search when the activity of the coding unit is less than the activity threshold, using the IntraBC coding cost to select an encoding mode from one of a plurality of encoding modes, encoding the coding unit using the selected encoding mode.

Abstract: A method for implementing a full sweep in a digital instrument cluster system without a graphical processing unit (GPU) is disclosed. The method includes displaying a static asset as background for displaying of dynamic assets that point to different position values on the static asset, sequentially retrieving each of a plurality of subsets of dynamic assets such that each subset provides position indicators with a different level of position granularity, wherein an order of retrieving each subset moves from a lowest granularity subset to a highest granularity subset until all of the plurality of subsets of dynamic assets have been retrieved, and performing a full sweep, prior to retrieving of the dynamic assets, by sequentially displaying the dynamic assets from a minimum position to a maximum position of the static asset, and back, the sequentially displaying being based on a highest available granularity of dynamic assets that have been retrieved.

Abstract: An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.

Abstract: A method for making a semiconductor device is provided. The method generally includes forming a package having a first plurality of leads extending from a first side of the package, the package disposed on a leadframe. The method generally includes making a first cut adjacent to a first side of a first lead of the first plurality of leads, the first side extending from the first side of the package. The method generally includes making a second cut adjacent to a second side of the first lead of the first plurality of the lead, the second side of the lead opposite the first side of the lead and extending from the first side of the package.

Abstract: In the described examples, a video integrated circuit (IC) chip includes a video input port (VIP) that receives a video stream. The video IC chip also includes a processing unit coupled to a non-transitory memory and is configured to detect the presence of a data stream provided to the VIP, cause the VIP to switch a target partition for the data stream from a given partition in the memory to another partition in the memory and to write the data stream to the other partition in the memory.

Abstract: An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.

Abstract: A method includes determining to send a data packet from a first transceiver to a second transceiver, the data packet configured according to a TCP, determining, at the first transceiver, to trigger the second transceiver to send an ACK packet according to a delayed ACK protocol, sending, from the first transceiver, the data packet with an additional packet responsive to determining the triggering of the ACK packet, and receiving, at the first transceiver, the ACK packet from the second transceiver responsive to the additional packet.

Abstract: A system on a chip (SoC) includes a first domain comprising a first processor configured to boot the SoC, and a first debug subsystem, a second domain comprising a second processor, the second domain configurable as either a safety domain or a general-purpose processing domain, and isolation circuitry between the first domain and the second domain. During boot-up of the SoC, the first processor provides code to the second domain which, when executed by the second processor, configures the second domain as either a safety domain or as a general-purpose processing domain.

Abstract: An integrated semiconductor device having a metallic element formed between a capacitor with and a doped region.

Abstract: In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.

Abstract: An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer; the semiconductor layer contains white space regions that include a PWELL region. An electronic device includes an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A sacrificial NWELL ring is adjacent to and separated from the NWELL region by a first gap.

Abstract: A driver includes a low-resistance charging path between a supply voltage rail and a first output node, a high-resistance charging path between the supply voltage rail and the first output node, an inverter coupled to the first output node and configured to enable and disable the low-resistance charging path, and a high-resistance discharging path between the first output node and a second output node. The first output node is coupled to a control terminal of a pass gate transistor in some implementations. The low-resistance charging path charges a voltage on the first output node to a threshold voltage of the pass gate transistor, and the high-resistance charging path charges the voltage on the first output node greater than the threshold voltage of the pass gate transistor. The high-resistance discharging path discharges the voltage on the first output node.

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.

Abstract: In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.

Abstract: A video codec for encoding a sequence of video frames divides a video frame area into number of row segments. The Video encoder selects a different set of row segments in each video frame in a set of video frames and encodes the selected set of row segments by intra-prediction. As a result, the selected part of the frame is intra-refreshed. The video codec limits the maximum value of the vertical global motion vector GMVy to zero and video codec adjust the number of row segments in the select set of row segments based on the height of the search range configured for the motion estimation. As a result, the video codec may not refer to an un-refreshed portion in the previous frame for encoding an already refreshed area of the current frame.

Abstract: A memory system includes a main memory, an auxiliary memory, a redundancy circuit, an extension control terminal, and a multiplexer. The main memory has a line width, and includes a write data input. The auxiliary memory has the same line width as the main memory, and includes a write data input. The redundancy circuit includes and input and an output. The input is coupled to the write data input of the main memory. The multiplexer includes a first input, a second input, a control input, and an output. The first input is coupled to the write data input of the main memory. The second input is coupled to the output of the redundancy circuit. The control input is coupled to the extension control terminal. The output of the multiplexer is coupled to the write data input of the auxiliary memory.

Abstract: An electronic circuit for controlling a power switch having a gate input, includes a signal generator configured to generate a gate driver input signal. The gate driver input signal has a first voltage during a first period of time, a second voltage during a second period of time, and toggles between the first voltage and the second voltage during a third period of time. The electronic circuit also includes a gate driver configured to receive the gate driver input signal and to provide a gate driver output signal based on the gate driver input signal. The signal generator is configured to cause the gate driver input signal to toggle during the third period of time such that the gate driver output signal has a third voltage during the second period of time, and an intermediate voltage that is less than the third voltage during the third period of time.

Abstract: A method includes receiving, by a first device in a stack, a command from a controller. The stack includes multiple devices. The method also includes dissipating, by the first device, an amount of power responsive to a difference between a longest response time for the devices to respond to the command, and a device response time for the first device to respond to the command.