Patents Assigned to Texas Instruments
  • Pulse width modulated amplifier
    Patent number: 11923813
    Abstract: A pulse width modulated (PWM) amplifier includes a synchronization logic circuit having a first input configured to receive a bridge control signal and having a second input configured to receive a clock signal. The synchronization logic circuit is configured to provide a slope switch signal and a reference switch signal. The PWM amplifier includes a ramp generator having a first input configured to receive a first voltage supply and having a second input configured to receive a second voltage supply and having a third input configured to receive the reference switch signal and having a fourth input configured to receive the slope switch signal. The ramp generator is configured to provide a ramp signal having a first slope responsive to the slope switch signal in a first state and having a second slope responsive to the slope switch signal in a second state and to provide the clock signal.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: March 5, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shaik Asif Basha, Mohit Chawla, Jasjot Singh Chadha
  • Systems and methods for regulating slew time of output voltage of DC motor drivers
    Patent number: 11923799
    Abstract: An apparatus for regulating a slew time of an output voltage of a motor driver system includes a gate current control circuit which has a first input coupled to receive a target slew time and a second input coupled to receive a slew time. The gate current control circuit provides an incremented gate current if the slew time is greater than the target slew time and provides a decremented gate current if the slew time is less than the target slew time. The apparatus includes a gate driver which has a first input coupled to receive a PWM signal and a second input coupled to receive the gate current. The gate driver provides a gate drive signal.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 5, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ashish Ojha, Krishnamurthy Shankar, Siddhartha Gopal Krishna, Priyank Anand, Ganapathi Hegde
  • Power converters with reduced ripple voltage
    Patent number: 11923762
    Abstract: An example circuit includes a supply comparator having a supply input, a supply reference input and a supply comparator output. The supply input is coupled to a supply input terminal, and the supply reference input is configured to receive a supply reference voltage. A controller has a comparator input, a high-side output and a low-side output. The comparator input is coupled to the supply comparator output. A high-side switch having a control input. The high-side switch is coupled between the supply input and a switch output terminal, and the high-side output is coupled to the control input of the high-side switch. A low-side switch has a control input. The low-side switch is coupled between the switch output terminal and a ground terminal, and the low-side output is coupled to the control input of the low-side switch.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: March 5, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sachin Sethumadhavan, Sayantan Gupta
  • RECESS LEAD FOR A SURFACE MOUNT PACKAGE
    Publication number: 20240071889
    Abstract: A lead for a surface mount package for a semiconductor device, and the surface mount package employing the same. In one example, the lead includes a central segment with a first side and a second side, a first extension from a portion of the first side, and a second extension from a portion of the second side. The lead also includes a recess extending through a portion of the central segment, the first extension and the second extension.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Applicant: Texas Instruments Incorporated
    Inventors: Naweed Anjum, Michael Gerald Amaro, Makarand Ramkrishna Kulkarni
  • MULTI-LEVEL VOLTAGE DETECTOR
    Publication number: 20240069073
    Abstract: In one example, a method comprises: receiving a voltage from a power converter, and generating a comparison result representing a comparison between the voltage and a voltage threshold. The method further comprises providing one of a first current reference or a second current reference to the power converter responsive to the comparison result, in which the first and second current references represent different current levels.
    Type: Application
    Filed: November 3, 2023
    Publication date: February 29, 2024
    Applicant: Texas Instruments Incorporated
    Inventor: Keliu Shu
  • finFET with lateral charge balance at the drain drift region
    Patent number: 11916142
    Abstract: A semiconductor device includes an extended drain finFET. The drain drift region of the finFET extends between a drain contact region and a body of the finFET. The drain drift region includes an enhanced portion of the drain drift region between the drain contact region and the body. The drain drift region also includes a first charge balance region and a second charge balance region laterally adjacent to, and on opposite sides of, the enhanced portion of the drain drift region. The enhanced portion of the drain drift region and the drain contact region have a first conductivity type; the body, the first charge balance region, and the second charge balance region have a second, opposite, conductivity type. The drain drift region is wider than the body.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventor: Ming-Yeh Chuang
  • Adaptive zero voltage switching (ZVS) loss detection for power converters
    Patent number: 11916495
    Abstract: A device is configured to detect a zero voltage switching (ZVS) circuit output that includes a hard switching signal. The hard switching signal includes a false signal and a spike signal. Thereafter, the device generates digital pulse signals that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal, and uses the digital pulse signal that corresponds to the spike signal for adjusting a timing of a pulse width modulation (PWM) switching cycle.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Hrishikesh Ratnakar Nene, Salil Chellappan, Zhong Ye
  • Type-2 compensation with reduced quiescent current
    Patent number: 11916486
    Abstract: A compensation circuit includes a tail current source, an error amplifier; a compensation resistor, and a voltage-to-current converter circuit. The tail current source is configured to generate a tail current. The error amplifier is coupled to the tail current source and biased by the tail current. The compensation resistor is coupled to the error amplifier. The voltage-to-current converter circuit is coupled to the error amplifier. The compensation resistor is configured to vary in resistance responsive to a change in the tail current, or the voltage-to-current converter circuit is configured to vary in transconductance responsive to the change in the tail current.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Anmol Sharma
  • Ceramic semiconductor device package with copper tungsten conductive layers
    Patent number: 11915986
    Abstract: A described example includes: a ceramic package having a board side surface and an opposite top side surface; a heat slug mounted to the board side surface of the ceramic package, forming a bottom surface in a die cavity; leads mounted to conductive lands on the ceramic package; sidewall metallization extending from the conductive lands and covering a portion of one of the sides of the ceramic package; copper tungsten alloy conductor layers formed in the ceramic package and spaced by dielectric layers; bond fingers formed of a conductor layer and extending to the die cavity; a semiconductor device mounted over the heat slug, and having bond pads on a device side surface facing away from a surface of the heat slug; electrical connections between bond pads on the semiconductor device and the bond fingers; and a lid mounted to the top side surface of the ceramic package.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ramlah Binte Abdul Razak, Hector Torres
  • Flip-flop with internal circuit for generating inflated low and high pulse width signals
    Patent number: 11916555
    Abstract: Example flip-flops comprise a circuit that receives a primary clock signal, generates a clock buffer signal having a series of pulses, each delayed by a set amount of time relative to a corresponding pulse of the primary clock signal, generates an intermediate clock signal based on the primary clock signal and the clock buffer signal, generates inflated low pulse width clock signals, each having a low pulse width that is greater than a low pulse width of the primary clock signal. Latch stages within example flip-flops include one or more components that are controlled by the inflated low pulse width clock signals. Example flip-flops include high-speed flip-flops and standard flip-flops. Larger circuits, such as a clock divider circuits, may incorporate multiple example high-speed flip-flops to improve performance.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Arnab Khawas, Badarish Subbannavar, Gokul Sabada
  • Driver device layouts
    Patent number: 11917734
    Abstract: An example circuit includes a substrate having a plurality of scan lines substantially orthogonal to a virtual centerline of the substrate. The circuit also includes a first driver integrated circuit (IC) on the substrate, the first driver IC including: a set of line switches coupled to a first set of the plurality of scan lines along a side of the first driver IC nearest the virtual centerline; a data output and a register. The circuit also includes a second driver IC on the substrate, the second driver IC including: a set of line switches coupled to a second set of the plurality of scan lines along a side of the second IC nearest the virtual centerline; and a data input coupled to the data output of the first driver IC.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shang Ding, Huibo Zhong, Bin Hu
  • Low power operational amplifier trim offset circuitry
    Patent number: 11916516
    Abstract: Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Nitin Agarwal, Kunal Karanjkar, Venkata Ramanan
  • Method and apparatus for arbitrary output shape processing of an image
    Patent number: 11915442
    Abstract: An apparatus and method for geometrically correcting an arbitrary shaped input frame and generating an undistorted output frame. The method includes capturing arbitrary shaped input images with multiple optical devices and processing the images, identifying redundant blocks and valid blocks in each of the images, allocating an output frame with an output frame size and dividing the output frame into regions shaped as a rectangle, programming the apparatus and disabling processing for invalid blocks in each of the regions, fetching data corresponding to each of the valid blocks and storing in an internal memory, interpolating data for each of the regions with stitching and composing the valid blocks for the output frame and displaying the output frame on a display module.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Rajasekhar Reddy Allu, Niraj Nandan, Mihir Narendra Mody, Gang Hua, Brian Okchon Chae, Shashank Dabral, Hetul Sanghvi, Vikram VijayanBabu Appia, Sujith Shivalingappa
  • Nonvolatile logic memory for computing module reconfiguration
    Patent number: 11914545
    Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Andreas Waechter, Mark Jung, Steven Craig Bartling, Sudhanshu Khanna
  • Feature point identification in sparse optical flow based tracking in a computer vision system
    Patent number: 11915431
    Abstract: A method for sparse optical flow based tracking in a computer vision system is provided that includes detecting feature points in a frame captured by a monocular camera in the computer vision system to generate a plurality of detected feature points, generating a binary image indicating locations of the detected feature points with a bit value of one, wherein all other locations in the binary image have a bit value of zero, generating another binary image indicating neighborhoods of currently tracked points, wherein locations of the neighborhoods in the binary image have a bit value of zero and all other locations in the binary image have a bit value of one, and performing a binary AND of the two binary images to generate another binary image, wherein locations in the binary image having a bit value of one indicate new feature points detected in the frame.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Deepak Kumar Poddar, Anshu Jain, Desappan Kumar, Pramod Kumar Swami
  • Low noise bandgap reference architecture
    Patent number: 11914412
    Abstract: In described examples, a circuit includes a first current mirror circuit. The first current mirror circuit is coupled to a power input terminal. A first stage is coupled to the first current mirror circuit, and a second stage is coupled to the first stage and to the first current mirror circuit. An amplifier is coupled to the first and second stages. The amplifier has first and second input terminals. The first input terminal is coupled to the first stage, and the second input terminal is coupled to the second stage. A second current mirror circuit is coupled to the first stage, the second stage and the amplifier.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sanjeev Praphulla Chandra Nyshadham, Subrato Roy
  • Accuracy trim architecture for high precision voltage reference
    Patent number: 11914410
    Abstract: Described embodiments include a circuit for controlling a voltage drop. The circuit includes a resistor coupled between an output voltage terminal and a reference voltage terminal. First, second and third switches each have respective first, second and third switch terminals. The respective second switch terminals are connected together and are coupled to the output voltage terminal. The respective third switch terminals are connected together and are coupled to the reference voltage terminal. A first transistor is coupled between a supply voltage terminal and the first switch. A second transistor is coupled between the supply voltage terminal and the second switch. A third transistor is coupled between the supply voltage terminal and the third switch. Control terminals of the first, second and third transistors are coupled to a gate control terminal.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Rajat Chauhan
  • Transient triggered active FET with surge immunity
    Patent number: 11916062
    Abstract: A microelectronic device has a protected line and a reference line, and an active field effect transistor (FET) coupled between the protected line and the reference line. The microelectronic device includes an electrostatic discharge (ESD) trigger circuit coupled to the gate of the active FET, to turn on the active FET when an ESD event occurs on the protected line. The microelectronic device further includes a transient detection circuit having a high bandwidth detector, an ESD detector, and an output driver. The ESD detector is configured to provide a CLEAR signal to the output driver when an ESD event occurs on the protected line. The output driver is configured to turn off the active FET when a voltage surge, which can damage the active FET, occurs on the protected line, but enable operation of the active FET by the ESD trigger circuit during an ESD event.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Xianzhi Dai, Rajkumar Sankaralingam
  • Segmented Schottky diode
    Patent number: 11916152
    Abstract: A semiconductor device includes a Schottky diode on a silicon-on-insulator (SOI) substrate. The Schottky diode includes a guard ring with a first guard ring segment contacting a barrier region on a first lateral side of the barrier region, and a second guard ring segment contacting the barrier region on a second, opposite, lateral side of the barrier region. The first and second guard ring segments extend deeper in the semiconductor layer than the barrier region. The Schottky diode further includes a drift region contacting the barrier region, and may include a buried layer having the same conductivity type as the barrier region, extending at least partway under the drift region. The barrier region is isolated from the substrate dielectric layer of the SOI substrate by an isolation region having the same conductivity type as the guard ring. A metal containing layer is formed on the barrier region.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventor: Zachary K. Lee
  • High reliability polysilicon components
    Patent number: 11916067
    Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee