Patents Assigned to Texas Instruments
  • Write streaming with cache write acknowledgment in a processor
    Patent number: 11921637
    Abstract: In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory controller. The memory controller has a memory pipeline. The memory controller is coupled to control the cache memory and communicatively coupled to the processor core. The memory controller is configured to receive the memory write requests from the processor core; schedule the memory write requests on the memory pipeline; and contemporaneously with scheduling respective ones of the memory write requests on the memory pipeline, send to the processor core a write acknowledgment confirming that writing of a data payload of the respective memory write request to the cache memory has completed.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: March 5, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, Timothy David Anderson, David Matthew Thompson
  • Transform and quantization architecture for video coding and decoding
    Patent number: 11924427
    Abstract: A method of encoding a video stream in a video encoder is provided that includes computing an offset into a transform matrix based on a transform block size, wherein a size of the transform matrix is larger than the transform block size, and wherein the transform matrix is one selected from a group consisting of a DCT transform matrix and an IDCT transform matrix, and transforming a residual block to generate a DCT coefficient block, wherein the offset is used to select elements of rows and columns of a DCT submatrix of the transform block size from the transform matrix.
    Type: Grant
    Filed: January 4, 2023
    Date of Patent: March 5, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Mangesh Sadafale, Madhukar Budagavi
  • Method and apparatus for dual multiplication units in a data path
    Patent number: 11921643
    Abstract: A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: March 5, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Mujibur Rahman, Timothy David Anderson, Soujanya Narnur
  • Semiconductor package with isolated heat spreader
    Patent number: 11923281
    Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: March 5, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anindya Poddar, Woochan Kim, Vivek Kishorechand Arora
  • Bipolar transistor with segmented emitter contacts
    Patent number: 11923442
    Abstract: An integrated circuit includes a transistor having a collector region, a base region and an emitter strip. The collector region includes layer of a semiconductor substrate doped with a dopant of a first conductivity type. The base region includes semiconductor layer over the semiconductor substrate, doped with a dopant of a second conductivity type. An emitter strip within the base region has a first width and is doped with a first dopant of the first conductivity type. A plurality of emitter contacts is located within the emitter strip. Each emitter contact has a second width less than the first width, and includes a second dopant of the first conductivity type. Each emitter contact is spaced from a nearest neighbor emitter contact by a portion of the emitter strip. In some examples the transistor has a common-emitter current gain greater than 3500.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: March 5, 2024
    Assignee: Texas Instruments Incorporated
    Inventor: Hiroshi Yasuda
  • Semiconductor device having tapered metal coated sidewalls
    Patent number: 11923320
    Abstract: A semiconductor device includes a semiconductor die having a top side surface comprising a semiconductor material including circuitry therein having bond pads connected to nodes in the circuitry, a bottom side surface, and sidewall surfaces between the top side surface and the bottom side surface. A metal coating layer including a bottom side metal layer is over the bottom side surface that extends continuously to a sidewall metal layer on the sidewall surfaces. The sidewall metal layer defines a sidewall plane that is at an angle from 10° to 60° relative to a normal projected from a bottom plane defined by the bottom side metal layer.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: March 5, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tomoko Noguchi, Mutsumi Masumoto, Kengo Aoya, Masamitsu Matsuura
  • Systems and methods for regulating slew time of output voltage of DC motor drivers
    Patent number: 11923799
    Abstract: An apparatus for regulating a slew time of an output voltage of a motor driver system includes a gate current control circuit which has a first input coupled to receive a target slew time and a second input coupled to receive a slew time. The gate current control circuit provides an incremented gate current if the slew time is greater than the target slew time and provides a decremented gate current if the slew time is less than the target slew time. The apparatus includes a gate driver which has a first input coupled to receive a PWM signal and a second input coupled to receive the gate current. The gate driver provides a gate drive signal.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 5, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ashish Ojha, Krishnamurthy Shankar, Siddhartha Gopal Krishna, Priyank Anand, Ganapathi Hegde
  • RECESS LEAD FOR A SURFACE MOUNT PACKAGE
    Publication number: 20240071889
    Abstract: A lead for a surface mount package for a semiconductor device, and the surface mount package employing the same. In one example, the lead includes a central segment with a first side and a second side, a first extension from a portion of the first side, and a second extension from a portion of the second side. The lead also includes a recess extending through a portion of the central segment, the first extension and the second extension.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Applicant: Texas Instruments Incorporated
    Inventors: Naweed Anjum, Michael Gerald Amaro, Makarand Ramkrishna Kulkarni
  • MULTI-LEVEL VOLTAGE DETECTOR
    Publication number: 20240069073
    Abstract: In one example, a method comprises: receiving a voltage from a power converter, and generating a comparison result representing a comparison between the voltage and a voltage threshold. The method further comprises providing one of a first current reference or a second current reference to the power converter responsive to the comparison result, in which the first and second current references represent different current levels.
    Type: Application
    Filed: November 3, 2023
    Publication date: February 29, 2024
    Applicant: Texas Instruments Incorporated
    Inventor: Keliu Shu
  • Feature point identification in sparse optical flow based tracking in a computer vision system
    Patent number: 11915431
    Abstract: A method for sparse optical flow based tracking in a computer vision system is provided that includes detecting feature points in a frame captured by a monocular camera in the computer vision system to generate a plurality of detected feature points, generating a binary image indicating locations of the detected feature points with a bit value of one, wherein all other locations in the binary image have a bit value of zero, generating another binary image indicating neighborhoods of currently tracked points, wherein locations of the neighborhoods in the binary image have a bit value of zero and all other locations in the binary image have a bit value of one, and performing a binary AND of the two binary images to generate another binary image, wherein locations in the binary image having a bit value of one indicate new feature points detected in the frame.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Deepak Kumar Poddar, Anshu Jain, Desappan Kumar, Pramod Kumar Swami
  • Ceramic semiconductor device package with copper tungsten conductive layers
    Patent number: 11915986
    Abstract: A described example includes: a ceramic package having a board side surface and an opposite top side surface; a heat slug mounted to the board side surface of the ceramic package, forming a bottom surface in a die cavity; leads mounted to conductive lands on the ceramic package; sidewall metallization extending from the conductive lands and covering a portion of one of the sides of the ceramic package; copper tungsten alloy conductor layers formed in the ceramic package and spaced by dielectric layers; bond fingers formed of a conductor layer and extending to the die cavity; a semiconductor device mounted over the heat slug, and having bond pads on a device side surface facing away from a surface of the heat slug; electrical connections between bond pads on the semiconductor device and the bond fingers; and a lid mounted to the top side surface of the ceramic package.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ramlah Binte Abdul Razak, Hector Torres
  • Accuracy trim architecture for high precision voltage reference
    Patent number: 11914410
    Abstract: Described embodiments include a circuit for controlling a voltage drop. The circuit includes a resistor coupled between an output voltage terminal and a reference voltage terminal. First, second and third switches each have respective first, second and third switch terminals. The respective second switch terminals are connected together and are coupled to the output voltage terminal. The respective third switch terminals are connected together and are coupled to the reference voltage terminal. A first transistor is coupled between a supply voltage terminal and the first switch. A second transistor is coupled between the supply voltage terminal and the second switch. A third transistor is coupled between the supply voltage terminal and the third switch. Control terminals of the first, second and third transistors are coupled to a gate control terminal.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Rajat Chauhan
  • Method and apparatus for arbitrary output shape processing of an image
    Patent number: 11915442
    Abstract: An apparatus and method for geometrically correcting an arbitrary shaped input frame and generating an undistorted output frame. The method includes capturing arbitrary shaped input images with multiple optical devices and processing the images, identifying redundant blocks and valid blocks in each of the images, allocating an output frame with an output frame size and dividing the output frame into regions shaped as a rectangle, programming the apparatus and disabling processing for invalid blocks in each of the regions, fetching data corresponding to each of the valid blocks and storing in an internal memory, interpolating data for each of the regions with stitching and composing the valid blocks for the output frame and displaying the output frame on a display module.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Rajasekhar Reddy Allu, Niraj Nandan, Mihir Narendra Mody, Gang Hua, Brian Okchon Chae, Shashank Dabral, Hetul Sanghvi, Vikram VijayanBabu Appia, Sujith Shivalingappa
  • Type-2 compensation with reduced quiescent current
    Patent number: 11916486
    Abstract: A compensation circuit includes a tail current source, an error amplifier; a compensation resistor, and a voltage-to-current converter circuit. The tail current source is configured to generate a tail current. The error amplifier is coupled to the tail current source and biased by the tail current. The compensation resistor is coupled to the error amplifier. The voltage-to-current converter circuit is coupled to the error amplifier. The compensation resistor is configured to vary in resistance responsive to a change in the tail current, or the voltage-to-current converter circuit is configured to vary in transconductance responsive to the change in the tail current.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Anmol Sharma
  • Driver device layouts
    Patent number: 11917734
    Abstract: An example circuit includes a substrate having a plurality of scan lines substantially orthogonal to a virtual centerline of the substrate. The circuit also includes a first driver integrated circuit (IC) on the substrate, the first driver IC including: a set of line switches coupled to a first set of the plurality of scan lines along a side of the first driver IC nearest the virtual centerline; a data output and a register. The circuit also includes a second driver IC on the substrate, the second driver IC including: a set of line switches coupled to a second set of the plurality of scan lines along a side of the second IC nearest the virtual centerline; and a data input coupled to the data output of the first driver IC.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shang Ding, Huibo Zhong, Bin Hu
  • finFET with lateral charge balance at the drain drift region
    Patent number: 11916142
    Abstract: A semiconductor device includes an extended drain finFET. The drain drift region of the finFET extends between a drain contact region and a body of the finFET. The drain drift region includes an enhanced portion of the drain drift region between the drain contact region and the body. The drain drift region also includes a first charge balance region and a second charge balance region laterally adjacent to, and on opposite sides of, the enhanced portion of the drain drift region. The enhanced portion of the drain drift region and the drain contact region have a first conductivity type; the body, the first charge balance region, and the second charge balance region have a second, opposite, conductivity type. The drain drift region is wider than the body.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventor: Ming-Yeh Chuang
  • Bandgap reference with input amplifier for noise reduction
    Patent number: 11914411
    Abstract: A bandgap reference circuit includes first through fourth bipolar junction transistors (BJTs). The base and collector of the first BJT are shorted together. The second BJT is coupled to the first BJT via a first resistor. The base of the third BJT is coupled to the base of the first BJT. The base and collector of the fourth BJT are coupled together and also are coupled to the base of the second BJT. A second resistor is coupled to the fourth emitter of the fourth BJT. A third resistor is coupled to the second resistor and to the emitter of the second BJT. An operational amplifier has a first input coupled to the first resistor and the collector of the second BJT, a second input coupled to the emitter of the third BJT and the collector of the fourth BJT, and an output coupled to the collectors of the first and third BJTs.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sandeep Shylaja Krishnan, Tallam Vishwanath, Akshay Yashwant Jadhav
  • Reduced complexity convolution for convolutional neural networks
    Patent number: 11915117
    Abstract: A method for convolution in a convolutional neural network (CNN) is provided that includes accessing a coefficient value of a filter corresponding to an input feature map of a convolution layer of the CNN, and performing a block multiply accumulation operation on a block of data elements of the input feature map, the block of data elements corresponding to the coefficient value, wherein, for each data element of the block of data elements, a value of the data element is multiplied by the coefficient value and a result of the multiply is added to a corresponding data element in a corresponding output block of data elements comprised in an output feature map.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Manu Mathew, Kumar Desappan, Pramod Kumar Swami
  • Codeword format for data storage
    Patent number: 11916570
    Abstract: The present disclosure generally relates to a codeword format for data storage and to methods and circuits for generating a codeword based on data to be written in memory and extracting data from a codeword read from memory. In an example, an integrated circuit includes a memory system and a controller circuit. The controller circuit is communicatively coupled to the memory system and is configured to: receive multi-bit data; generate a codeword based on the multi-bit data; and transmit to the memory system the codeword for writing to memory. The codeword has a format that includes first bit positions for the multi-bit data, second bit positions for a bitwise inversion of the multi-bit data, a third bit position for an odd parity value, and a fourth bit position for an even parity value. The odd and even parity values indicate an odd and even parity, respectively, of the multi-bit data.
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Dominik Stefan Gerl, Annabelle Arnold
  • Low power operational amplifier trim offset circuitry
    Patent number: 11916516
    Abstract: Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Nitin Agarwal, Kunal Karanjkar, Venkata Ramanan