Abstract: A method of determining a summation of pixel characteristics for a rectangular region of a digital image includes determining if a base address for a data element in an integral image buffer is aligned for an SIMD operation by a processor embedded in an electronic assembly configured to perform Haar-like feature calculations. The data element represents a corner of the rectangular region of an integral image. The integral image is a representation of the digital image. The integral image is formed by data elements stored in the integral image buffer. The data element is loaded from the integral image buffer to the processor when the base address is aligned for the SIMD operation. An offset data element of an offset integral image is loaded from an offset integral buffer when the base address is non-aligned for the SIMD operation. The offset data element represents the corner of the rectangular region.

Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.

Abstract: An integrated circuit with a micro inductor or with a micro transformer with a magnetic core. A process of forming an integrated circuit with a micro inductor with a magnetic core. A process of forming an integrated circuit with a micro transformer with a magnetic core.

Abstract: Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.

Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

Abstract: The PRPG provides the test stimulus to the circuit, but it can only generate a finite number of care-bits from any given input seed which limits the maximum coverage that can be achieved. The only way to increase the coverage is to provide additional seed input data to the PRPG. The on-chip one time only programmable eFuse is used to store new PRPG seed data inputs and corresponding MISR output signature data for comparison. An XOR circuit option on the output of the MISR is operable to further compress the output data.

Abstract: In some examples, an electrostatic discharge (ESD) device comprises an insulated-gate bipolar transistor (IGBT) comprising a source terminal, an anode terminal, a gate terminal, and a body terminal; and at least one reverse bias device comprising a first terminal and a second terminal, wherein the first terminal couples to the source terminal and the second terminal couples to the body terminal.

Abstract: A semiconductor device has a protected line connected to a ground line by a triggered clamp. A variable shunt, which includes a depletion mode JFET, is connected between the protected line and the ground line, in parallel with the triggered clamp. The depletion mode JFET is formed in a substrate of the semiconductor device. The channel of the depletion mode JFET provides a resistive path for the variable shunt when the semiconductor device is unpowered, to dissipate charge from the powered line after an ESD event. When the semiconductor device is operated, that is, powered up, the gate of the depletion mode JFET may be biased to turn off the channel, and so reduce impairment of operation of the semiconductor device.

Abstract: Disclosed examples include isolated dual active bridge (DAB) DC to DC converters with first and second bridge circuits, a transformer with a sense coil, and a secondary side control circuit to provide secondary side switching control signals to regulate an output voltage or current signal by controlling a phase shift angle between switching transitions of the secondary side switching control signals and switching transitions of a secondary side clock signal, where the secondary side control circuit includes a clock recovery circuit to synchronize the secondary side clock signal to transitions in a sense coil voltage signal of the sense coil.

Abstract: These teachings apply with respect to a direct current (DC)-output converter and provide for adjusting a number of switching pulses per burst cycle as a function, at least in part, of converter output loading. This adjustment can be made by controlling burst frequency with respect to at least one predetermined threshold frequency. The predetermined threshold frequency can comprise a non-audible frequency such that the number of switching pulses is adjusted to prevent the burst frequency from itself constituting an audible signal. The adjustment of the number of switching pulses per burst cycle may only occur when the output loading is less than a predetermined level of loading. These teachings may also provide for clamping the pulse frequency for the pulses in each burst package to a particular value when dynamically controlling the number of pulses in each burst package. The aforementioned particular value may constitute, for example, a highest available switching frequency.

Abstract: Frequency synthesis is based on phase synchronizing PLL output across REFERENCE and VCO clock domains (including outputs for multiple PLLs), based on an input (REF-Domain) SYNC signal (phase timing reference). A frequency synthesizer includes a VCO to generate VCO_clk and a PLL output circuit, such as a channel divider, to generate PLL_OUT based on VCO_clk (in the VCO-Domain). The VCO loop includes a PD to phase compare an input PD_clock based on REF_CLK, and a VCO feedback signal based on divided VCO_clk (NDIV_out). SYNC alignment circuitry generates a SYNC alignment signal based on SYNC, PD_clk, and NDIV_out (REF-Domain), which is used to synchronize the PLL output circuit and PLL_OUT to SYNC. If a reference divider generates PD_clk, the SYNC alignment circuitry generates a reset to SYNC-align the reference divider. If the VCO loop uses fractional divide, the SYNC alignment circuitry resets the fractional modulator to a known sequence.

Abstract: An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory; a low energy accelerator processor configured to execute instruction words received on the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, wherein each of the execution units is configured to perform operations responsive to retrieved instruction words; and a data register file comprising a set of data registers coupled to the plurality of execution units, wherein the registers are coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.

Abstract: A controller including a voltage synthesizer for a switching regulator includes a synthesizer input to be coupled to an input of the regulator. First and second replica switching transistors are connected at a first node. A resistor couples between the first node and a second node, and a capacitor couples between the second node and ground. A transconductance stage compares a voltage sampled onto the capacitor to the output voltage of the regulator and generates an output signal in response to the comparison. A first switch couples between first and second inputs of the transconductance stage. The first switch is turned on during each cycle of operation of the voltage synthesizer to reset the capacitor voltage to the output voltage of the regulator.

Abstract: A microelectronic device having an n-type buried layer (NBL) is formed by forming a thin screen layer on the top surface of the substrate. Antimony is implanted through the screen layer exposed by an implant mask into the substrate; the implant mask blocks antimony from the substrate outside the NBL area. The implant mask is removed, leaving the screen layer, which has the same thickness over the NBL area and the area outside the NBL, on the surface. Silicon dioxide is formed during an anneal/drive process, both in the NBL area and outside the NBL area. Slightly more silicon dioxide is formed in the NBL area, consuming more silicon there and so forming a shallow silicon recess. An epitaxial layer is grown on the top surface of the substrate. A structure for the microelectronic device is also disclosed.

Abstract: A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect. A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect using via priority groups.

Abstract: An apparatus comprises a voltage supply configured to provide an input voltage, a buck-boost converter coupled to the voltage supply and comprising an inductor, and a buck-boost controller coupled to the power supply and the buck-boost converter. The buck-boost controller comprises a mode controller coupled to the buck-boost converter and a comparator coupled to the mode controller and the buck-boost converter. The comparator is configured to compare an error signal based on an output voltage of the buck boost-converter to an output current of the inductor to produce a control signal. The mode controller is configured to control the output voltage at least in part according to the control signal.

Abstract: The present disclosure relates to an apparatus comprising at least one sensing capacitor and a controller, wherein the controller is configured to receive a signal from the at least one sensing capacitor indicative of a change of charge of the sensing capacitor, and wherein the controller is configured to determine an amount of force applied to the sensing capacitor, an acceleration of the sensing capacitor, a torsion of the sensing capacitor, a vibration of the sensing capacitor or a pulling force applied to the sensing capacitor based on the change of charge of the at least one sensing capacitor.

Abstract: A voltage/current regulator supplying controlled current with PVT headroom adjustment. In an example application, an LED backlight driver controls ILED string current, and controls a voltage regulator supplying VOUT string voltage with sufficient headroom voltage VHDRM to supply the ILED string current. The LED driver controls ILED string current with an MLED current control transistor, including gate drive referenced to a reference voltage VREF. VOUT/VHDRM are adjusted for PVT operating conditions by generating a replica/reference current ILED/RATIO (proportional to ILED string current) with a replica current control transistor MLED/RATIO based on VREF. ILED/RATIO is mirrored to a second replica MLED/RATIO transistor that saturates at a PVT_REF reference voltage corresponding to a minimum voltage that can supply the required ILED current (as represented by the ILED/RATIO replica/reference current), accounting for PVT operating conditions.

Abstract: A method for decoding a compressed video bit stream in a video decoder to recover a video sequence, the video decoder including a plurality of decoder processing cores is provided. The method includes determining that a picture is encoded in the compressed bit stream as a pre-determined number of independently encoded sub-pictures, and dispatching a first encoded sub-picture of the pre-determined number of sub-pictures to a first decoder processing core of the plurality of decoder processing cores and a second encoded sub-picture of the pre-determined number of sub-pictures to a second decoder processing core of the plurality of decoder processing cores, wherein the first encoded sub-picture and the second encoded sub-picture are independently decoded in parallel on the respective first and second decoder processing cores.

Abstract: A disclosed method includes computing, for each of a plurality of values of at least one type of error parameter, a distance traveled for each of a plurality of directions of travel. The method includes selecting, from the plurality of values of the at least one type of error parameter, a value that provides a greatest distance traveled for any of the plurality of directions of travel relative to the unselected ones of the plurality of values. The method further includes applying the selected value of the at least one type of error parameter to gyroscopic sensor data, and then determining navigation information based on the gyroscopic sensor data with the selected value of the at least one type of error parameter applied.