Abstract: Systems and methods for application profiles and device classes in power line communications (PLCs) are described. In some embodiments, a PLC device has the device class defined by a PHY layer and may include a processor and a memory coupled to the processor. The memory may be configured to store program instructions, which may be executable by the processor to cause the PLC device to communicate with a higher-level PLC apparatus over a power line using a frequency band. The frequency band may be selected based upon an application profile and/or a device class associated with the PLC device. In some implementations, the higher-level PLC apparatus may include a PLC gateway or a data concentrator, and the PLC device may include a PLC modem or the like. Examples of application profiles include access communications, in-premises connectivity, AC charging, and/or DC charging. Device classes may represent a minimum communication data rate and/or an operating frequency band restriction of the PLC device.

Abstract: In some embodiments, an analog-to-digital converter (ADC) comprises a loop filter configured to produce an error signal based on a difference between an analog input signal and a feedback signal. The ADC also comprises a main comparator set comprising one or more main comparators, the main comparator set configured to digitize the error signal and further configured to drive a main digital-to-analog converter (DAC). The ADC further comprises an auxiliary comparator set comprising a plurality of auxiliary comparators, the auxiliary comparator set configured to digitize the error signal when the ADC is in a runaway state and further configured to drive an auxiliary DAC to bring the error signal into a predetermined range.

Abstract: An integrated device includes a substrate having a semiconductor surface layer including functional circuitry, a lower metal stack on the semiconductor surface layer, an interlevel dielectric (ILD) layer on the lower metal stack, a top metal layer providing AMR contact pads and bond pads coupled to the AMR contact pads in the ILD layer. An AMR device is above the lower metal stack lateral to the functional circuitry including a patterned AMR stack including a seed layer, an AMR material layer, and a capping layer, wherein the seed layer is coupled to the AMR contact pads by a coupling structure. A protective overcoat (PO layer) is over the AMR stack. There are openings in the PO layer exposing the bond pads.

Abstract: An integrated circuit may include a metal gate which extends over an active area and onto an isolation dielectric layer. A conductive spline is formed on the metal gate, extending on the metal gate over at least a portion of the isolation dielectric layer, and extending on the metal gate for a length at least four times a width of the metal gate.

Abstract: A method of fabricating ICs including thin film resistors (TFRs) depositing a dielectric liner layer on a substrate including a semiconductor surface having a plurality of IC die formed therein each including functional circuitry comprising a plurality of interconnected transistors. A TFR layer comprising chromium (Cr) is deposited on the dielectric liner layer. The TFR layer is plasma treated with atomic nitrogen and atomic hydrogen. A dielectric capping layer is deposited on the TFR layer after the plasma treating. A pattern is formed on the capping layer, and the TFR layer is etched to form at least one resistor that comprises the TFR layer.

Abstract: A synchronous rectifier controller integrated circuit. The synchronous rectifier controller integrated circuit comprises a continuous current mode (CCM) detection circuit configured to detect CCM operation based on sensing a voltage at a pre-defined point in a rectification cycle; a multiplexer having a first reference voltage signal input, a second reference voltage signal input, an output, and a selector input coupled to the CCM detection circuit; and a gate voltage driver circuit coupled to the output of the multiplexer.

Abstract: In some examples, a shunt regulator includes a plurality of selection pins configured to receive a digital signal. The shunt regulator also includes an internal reference voltage selection circuit coupled to the plurality of selection pins, the internal reference voltage selection circuit configured to select a first internal reference voltage of the shunt regulator based on the digital signal. The shunt regulator further includes a soft ramp control circuit coupled to the internal reference voltage selection circuit and to a soft ramp control pin that is configured to carry a second internal reference voltage, the soft ramp control circuit configured to compare the first and the second internal reference voltages to generate a soft ramp control output signal.

Abstract: The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.

Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

Abstract: The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states.

Abstract: An etchant for simultaneously etching NiFe and AlN with approximately equal etch rates that comprises phosphoric acid, acetic acid, nitric acid and deionized water. Alternating layers of NiFe and AlN may be used to form a magnetic core of a fluxgate magnetometer in an integrated circuit. The wet etch provides a good etch rate of the alternating layers with good dimensional control and with a good resulting magnetic core profile. The alternating layers of NiFe and AlN may be encapsulated with a stress relief layer. A resist pattern may be used to define the magnetic core geometry. The overetch time of the wet etch may be controlled so that the magnetic core pattern extends at least 1.5 um beyond the base of the magnetic core post etch. The photo mask used to form the resist pattern may also be used to form a stress relief etch pattern.

Abstract: In accordance with disclosed embodiments, a first power line communication (PLC) device connected to a PLC network includes channel control logic that assigns a first channel of the PLC network for transmission on a power line of PLC data packets between the first PLC device and a second PLC device connected to the PLC network and assigns a second channel of the PLC network for transmission on the power line of PLC data packets between the first PLC device and the third PLC device connected to the PLC network. The PLC device includes a transceiver that receives and transmits PLC data packets on the PLC network and which operates as a bridge device that communicates on both the first and second channels to pass PLC data packets between the second PLC device and the third PLC device.

Abstract: A circuit includes a current sensor to sense a switching current flowing at input side of a switching DC-DC converter. An output capacitor filters an output voltage at an output side of the switching DC-DC converter. A feed-forward circuit passes a portion of the sensed switching current to a feedback path on the output side of the switching DC-DC converter simulating a changing effective series resistance (ESR) of the output capacitor to facilitate operating stability in the switching DC-DC converter.

Abstract: A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.

Abstract: An image processing system includes a processor and optical flow (OF) determination logic for quantifying relative motion of a feature present in a first frame of video and a second frame of video that provide at least one of temporally and spatially ordered images with respect to the two frames of video. The OF determination logic configures the processor to implement performing OF estimation between the first frame and second frame using a pyramidal block matching (PBM) method to generate an initial optical flow (OF) estimate at a base pyramid level having integer pixel resolution, and refining the initial OF estimate using at least one pass of a modified Lucas-Kanade (LK) method to provide a revised OF estimate having fractional pixel resolution.

Abstract: A multiphase power regulator includes a plurality of phases coupled in parallel to provide a load current as a combination of phase currents at an output voltage, each phase including at least one power transistor switched to provide a respective phase current based at least in part on a comparator output signal, and a current-sense low pass filter to sense the phase current. The regulator further includes a gm stage to generate the current set point voltage based at least in part on the output voltage, a comparator to compare a voltage from the current-sense low pass filters to the current set point voltage and a current set point adjustment circuit to provide an auxiliary control signal to decrease the current set point voltage responsive to a change in comparator output and then to increase the current set point voltage responsive to another change in comparator output.

Abstract: This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

Abstract: Disclosed examples include methods, integrated circuits and switch circuits including a driver circuit and a silicon transistor or other current source circuit coupled with a gallium nitride or other high electron mobility first transistor, where the driver operatives in a first mode to deliver a control voltage signal to the first transistor, and in a second mode in response to a detected overvoltage condition associated with the first transistor to control the current source circuit to conduct a sink current from the first transistor to affect a control voltage to at least partially turn on the first transistor.

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Abstract: A surrounded emitter bipolar device includes a substrate having a p-epitaxial (p-epi) layer thereon, and a p-base in the p-epi layer. A two dimensional (2D) array of p-base contacts (base units) include the p-base, wherein each base unit includes an outer dielectric structure surrounding an inner dielectric isolation ring. The inner dielectric isolation ring surrounds an n region (n+moat). A first portion of the n+moats are collector (C) units, and a second portion of the n+moats are emitter (E) units. Each of the E units is separated from a nearest neighbor E unit by a C unit.