Abstract: Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.

Abstract: Control circuits and methods to operate a switch of a DC-DC converter, including an output circuit to turn the switch off to control a peak inductor current in a given switching control cycle, and a modulation circuit to implement transition mode (TM) or continuous conduction mode (CCM) operation for a given switching control cycle by causing the output circuit to turn the switch on in response to an earlier one of a first signal, that represents an inductor current of the DC-DC converter, decreasing to a reference voltage that represents a zero crossing of the inductor current for the TM operation or the first signal decreasing to a valley reference signal that represents a non-zero value of the inductor current for the CCM operation.

Abstract: The disclosure provides an input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a cutoff circuit that receives a first invert signal, the IO supply voltage, a bias voltage and a pad voltage. An output stage is coupled to the cutoff circuit. The output stage receives a first signal, a second signal and the bias voltage. A pad is coupled to the output stage, and a voltage generated at the pad is the pad voltage. The cutoff circuit and the output stage maintain the pad voltage at logic high when the IO supply voltage transition below a defined threshold.

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

Abstract: A system can include a given video processing engine to determine an estimated Quantization Parameter (QP) for a given row of Coding Tree Units (CTUs) in a frame of a video. The given processing engine can also encode the given row of CTUs in the frame of the video. A CTU in the given row of CTUs can be encoded with a QP equal to the estimated QP. The system can include another video processing engine to determine an estimated QP for another row of CTUs of the frame of the video. The other processing engine can also set a running QP to the estimated QP for the given row of CTUs prior to the given video processor encoding a last CTU in the given row of CTUs. The other processing engine can further encode the other row of CTUs. CTUs encoded by the given video processing engine and the other video processing engine can be stored in a non-transitory machine readable medium.

Abstract: Methods are provided for inter-prediction candidate index coding independent of the construction of the corresponding inter-prediction candidate list, i.e., a merging candidate list or an advanced motion vector predictor list. A maximum allowed number of inter-prediction candidates for an inter-prediction candidate list is used for encoding the inter-prediction candidate index in an encoded bit stream. The maximum allowed number may be pre-determined or may be selected by the encoder and encoded in the bit stream. A decoder may then decode the index using the maximum allowed number of inter-prediction candidates independent of the construction of the corresponding inter-prediction candidate list.

Abstract: Methods and circuitry for driving a device through drive cycles wherein each drive cycle has a plurality of drive stages are disclosed. An example of the circuitry includes an output for coupling the circuitry to the device and a plurality of drive slices coupled in parallel to the output. Control circuitry selectively activates individual drive slices in the plurality of drive slices during each stage of a drive cycle.

Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.

Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.

Abstract: A method of determining angular position (0) of a rotor of an N-phase permanent magnet motor (PMM). A processor having an associated stored angular position determination (APD) algorithm is programmed to implement the algorithm to cause an associated motor controller to execute steps including forcing one vector at a time a phase vector set of current or voltage vectors to stator terminals of windings for the N-phases a positive and negative magnitude vector, wherein the vector magnitude is sufficiently small to not move the rotor, and a time duration for the forcing current or voltage vectors is essentially constant. The resulting stator current or voltage levels are measured for each current or voltage vector. An N-dimension current vector or voltage vector is generated from superposition of the resulting stator current levels or resulting stator voltage levels. The N-dimension current vector or voltage vector is used to determine angular position.

Abstract: An integrated circuit (IC) package includes an IC die and a wave channel that electrically couples the IC die to a solder ball array. The wave channel is configured to resonate at an operating frequency band of the IC die.

Abstract: To enable lossless compression, an auxiliary bitmap is used to provide side information about the graph bitmap. Each bit in the auxiliary bitmap represents a word in the graph bitmap. A zero bit in the auxiliary bitmap means that the corresponding word in the graph bitmap is not transmitted. Therefore, it is set to the default value, ?, during decompression. This default value could be either an all-zeros word, or all-ones word depending on the BFS step. A one bit in the auxiliary bitmap means that the corresponding word in the graph bitmap is transmitted.

Abstract: A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

Abstract: A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed.

Abstract: A microelectronic device is formed by thinning a substrate of the microelectronic device from a die attach surface of the substrate, and forming a copper-containing layer on the die attach surface of the substrate. A protective metal layer is formed on the copper-containing layer. Subsequently, the copper-containing layer is attached to a package member having a package die mount area. The protective metal layer may optionally be removed prior to attaching the copper-containing layer to the package member. Alternatively, the protective metal layer may be left on the copper-containing layer when the copper-containing layer is attached to the package member. A structure formed by the method is also disclosed.

Abstract: A method of generating a high dynamic range (HDR) image is provided that includes capturing a long exposure image and a short exposure image of a scene, computing a merging weight for each pixel location of the long exposure image based on a pixel value of the pixel location and a saturation threshold, and computing a pixel value for each pixel location of the HDR image as a weighted sum of corresponding pixel values in the long exposure image and the short exposure image, wherein a weight applied to a pixel value of the pixel location of the short exposure image and a weight applied to a pixel value of the pixel location in the pixel long exposure image are determined based on the merging weight computed for the pixel location and responsive to motion in a scene of the long exposure image and the short exposure image.

Abstract: An amplifier includes a first transistor coupled to a first voltage source node and a second transistor coupled to a second voltage source node. The first and second transistors also couple together at an intermediate node. The amplifier further includes a third transistor coupled to the intermediate node and a fourth transistor coupled to the third transistor at a positive output node of the amplifier. Further, the amplifier includes a fifth transistor coupled to the intermediate node and a sixth transistor coupled to the fifth transistor at a negative output node of the amplifier.

Abstract: A circuit includes a zero current detector (ZCD) circuit that senses an inductor current of an inductor and generates signal pulses indicating when an increasing cycle of the inductor current crosses a predetermined current value and when a decreasing cycle of the inductor current crosses the predetermined current value. A sync control provides a control signal specifying one of the signal pulses corresponding to the increasing or decreasing cycle of the inductor current. A sync selector circuit generates a sync pulse representing the signal pulse from the ZCD in response to the control signal. The sync pulse triggers a timing adjustment for a switch device.

Abstract: A WLAN device includes a processor implementing a MAC layer and a PHY layer which is coupled to a transceiver including a receive (Rx) chain and a transmit (Tx) chain that is coupled to an antenna. A preamble decode-based receive suspend algorithm has software stored in a memory that is implemented by the processor or by hardware including digital logic. The algorithm responsive to receiving a packet including a Physical Layer Convergence Protocol (PLCP) header, a MAC header, and data, is for analyzing a length field in the PLCP header to determine whether the packet is an undesignated packet and whether there is sufficient time remaining for implementing a turning off and then back on of an analog portion of the Rx chain to avoid missing a next packet. If the undesignated packet and sufficient time are present, the analog portion of the Rx chain is turned off.

Abstract: A power factor correction (PFC) integrated circuit having a feed forward circuit. The feed forward circuit comprises a first current source, a second current source, and a third current source, a first bi-polar junction transistor (BJT), a second BJT, a third BJT, and a fourth BJT coupled together in a translinear cell, where the first current source is coupled to the first BJT, the second current source is coupled to the second BJT, and the third current source is coupled to the third BJT, a biasing network coupled to the first BJT and to the second BJT and configured to maintain equal collector-to-emitter voltage across the first BJT and the second BJT, where the feed forward circuit is configured to output a current based on a current of the first current source, a current of the third current source, and a current of the second current source.