Patents Assigned to Texas Instruments
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Patent number: 6801958Abstract: According to one embodiment of the present invention, a system (10) for data transfer is disclosed that comprises a transfer memory (24) having one or more buffers (40, 42, 44, 46, and 48). Accessing units comprising direct memory access units (20 and 22) are coupled to the transfer memory (24) and are operable to access the transfer memory (24). Pointers (50, 52, and 54) stored in the transfer memory (24) direct the accessing units (20 and 22) to selected ones of the buffers (44, 46, and 48) such that no two accessing units (20 and 22) are simultaneously accessing one buffer (44, 46, and 48). More specifically, the pointers (50, 52, and 54) may also direct a memory control unit (30) to a buffer that is not being accessed by an accessing units (20 and 22). According to one embodiment of the present invention, a method for data transfer is disclosed. First, a transfer memory (24) comprising one or more buffers (40, 42, 44, 46, and 48) is provided.Type: GrantFiled: December 6, 2000Date of Patent: October 5, 2004Assignee: Texas Instruments IncorporatedInventor: Robert Glenn Gugel
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Patent number: 6801588Abstract: A combined channel and entropy decoder is provided that achieves a significant bit-error rate improvement using likelihood values (61) instead of conventional bits. The likelihood values are stored in a buffer (62). A unique code-word is searched in the bit pattern or in the likelihood value. When a unique code-word is found at the identifier (63), candidate code-words are loaded into computation units where each unit computes code-word likelihood for a given code-word bit pattern. The code-word likelihood values are compared and the selected code information is fed back to the code-word controller 67 to proceed to the next-step decoding.Type: GrantFiled: September 22, 2000Date of Patent: October 5, 2004Assignee: Texas Instruments IncorporatedInventor: Hirohisa Yamaguchi
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Patent number: 6801461Abstract: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.Type: GrantFiled: December 17, 2001Date of Patent: October 5, 2004Assignee: Texas Instruments IncorporatedInventors: Kuong Hua Hii, Danny R. Cline, Theo J. Powell
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Patent number: 6801075Abstract: A base current compensation circuit is configured for injecting base current to the base of a transistor device to compensate for the lost current demanded by a transistor base. The base current compensation circuit is configured to inject current into the base of the transistor without the headroom requirements, as well as being less complex than other approaches. An exemplary base current compensation circuit comprises a sampling circuit and a current mirror feedback circuit configured for providing multiples of the base current demanded by the transistor device.Type: GrantFiled: October 2, 2002Date of Patent: October 5, 2004Assignee: Texas Instruments IncorporatedInventors: David A. Gammie, Jeffery B. Parfenchuck, Jerry L. Doorenbos
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Patent number: 6801499Abstract: A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time information with a source rate (s11) greater than zero kilobits per second, and a time or path or combined time/path diversity rate (d11), the amount of diversity (d11) initially being at least zero kilobits per second. The process sends the packets, thereby resulting in a quality of service QoS, and optionally obtains at the sender (311) a measure of the QoS. Rate/diversity adaptation decision may be performed at receiver (361′) instead. Another step compares the QoS with a threshold of acceptability (Th1), and when the QoS is on an unacceptable side of said threshold (Th1) increases the diversity rate (d11 to d22) and sends not only additional ones of the packets of real-time information but also sends diversity packets at the diversity rate as increased (d22).Type: GrantFiled: December 14, 1999Date of Patent: October 5, 2004Assignee: Texas Instruments IncorporatedInventors: Krishnasamy Anandakumar, Vishu R. Viswanathan, Alan V. McCree
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Patent number: 6801532Abstract: A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time information with a source rate (s11) greater than zero kilobits per second, and a time or path or combined time/path diversity rate (d11), the amount of diversity (d11) initially being at least zero kilobits per second. The process sends the packets, thereby resulting in a quality of service QoS, and optionally obtains at the sender (311) a measure of the QoS. Rate/diversity adaptation decision may be performed at receiver (361′) instead. Another step compares the QoS with a threshold of acceptability (Th1), and when the QoS is on an unacceptable side of said threshold (Th1) increases the diversity rate (d11 to d22) and sends not only additional ones of the packets of real-time information but also sends diversity packets at the diversity rate as increased (d22).Type: GrantFiled: December 14, 1999Date of Patent: October 5, 2004Assignee: Texas Instruments IncorporatedInventors: Krishnasamy Anandakumar, Vishu R. Viswanathan, Alan V. McCree
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Patent number: 6801567Abstract: A frequency bin method of carrier frequency acquisition uses a plurality of predetermined carrier frequency offset bins. A single bin is selected from among the plurality of bins. A local VCO is then adjusted to remove the carrier frequency offset associated with the single selected bin. Carrier frequency acquisition is then attempted using the adjusted VCO. If successful, the receiver enters its steady state operating mode. If unsuccessful, a new bin is selected and the VCO is again adjusted using the new carrier frequency offset associated with the newly selected bin. The process is repeated until successful communication is achieved in association with a properly adjusted VCO.Type: GrantFiled: March 30, 2000Date of Patent: October 5, 2004Assignee: Texas Instruments IncorporatedInventors: Timothy M. Schmidl, Sundararajan Sriram
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Patent number: 6800547Abstract: A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer (520) which invades open surface pores (514) of xerogel (510).Type: GrantFiled: July 5, 2001Date of Patent: October 5, 2004Assignee: Texas Instruments IncorporatedInventors: Jiong-Ping Lu, Changming Jin
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Publication number: 20040189875Abstract: In one embodiment, a method for processing a video signal includes: (1) receiving and storing luminance and chrominance information for each pixel in a first portion of the signal; (2) receiving luminance and chrominance information for each pixel in a second portion of the signal; (3) determining an estimated motion vector for each particular pixel of the second portion by comparing the luminance and chrominance information of the particular pixel to the stored luminance and chrominance information for one or more pixels in a search area of the first portion to determine a pixel in the search area that most closely matches the particular pixel and determining the estimated motion vector according to the particular pixel and the most closely matching pixel; (4) using the estimated motion vector to access the chrominance information for the most closely matching pixel; (5) using a three-dimensional comb filter to filter the chrominance information for the particular pixel and for the most closely matching pixeType: ApplicationFiled: March 31, 2003Publication date: September 30, 2004Applicant: Texas Instruments IncorporatedInventors: Fan Zhai, Karl H. Renner
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Publication number: 20040188752Abstract: A method of reducing dopant losses is provided. The method includes providing a transistor structure having a first region, implanting a dopant into the first region, depositing a control layer adjacent the first region, and performing a first annealing process on the transistor structure. The control layer is operable to prevent at least a portion of the dopant in the first region from diffusing out of the first region toward the control layer during the first annealing process.Type: ApplicationFiled: March 31, 2003Publication date: September 30, 2004Applicant: Texas Instruments IncorporatedInventor: Donald S. Miles
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Publication number: 20040191976Abstract: The rate at which the output of an output buffer changes is determined, and the strength of the output buffer is modified until the rate of change reaches a desired rate. The desired rate may be selected such that strength of the output buffer matches the then existing load. In other words, the strength may be only as much as needed to drive the then existing load. As a result, effects such as switching noise may be considerably reduced.Type: ApplicationFiled: March 27, 2003Publication date: September 30, 2004Applicant: Texas Instruments IncorporatedInventors: Anand Hariraj Udupa, Visvesvaraya Pentakota Appala
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Publication number: 20040194040Abstract: A method of cross-mapping integrated circuit (“IC”) elements nets in a IC and/or directing a probe to points on an IC to achieve minimal interference from adjacent structures is disclosed. The method of provides a more streamlined approach than referencing points from a physical layout representation of the IC to the actual IC being tested. The improved correlation between the actual packaged IC and the layout of the IC is accomplished using artificial locator cells. Preferably, the artificial locator cells are generated from mathematical operations of the extracted version of the layout, and they further provide coordinate information for where minimal interference from adjacent structures may be accomplished. Artificial locator cells may be generated from a layout representing a hierarchical representation or alternately each element that is instantiated from a reference library may already have artificial locator cells included.Type: ApplicationFiled: March 24, 2003Publication date: September 30, 2004Applicant: Texas Instruments IncorporatedInventors: Hemant Joshi, David A. Thomas, John Bach, Rand B. Carawan
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Publication number: 20040194007Abstract: A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit (38) is disclosed. The LDPC code is arranged as a parity check matrix (H) whose rows and columns represent check sums and input nodes, respectively. The parity check matrix is grouped into subsets of check sum rows, in which the column weight is a maximum of one. The decoder circuitry includes a parity check value estimate memory (52). Adders (54) generate extrinsic estimates, from immediately updated input node probability estimates, and the extrinsic estimates are applied to parity check update circuitry (56) for generating new parity check sum value estimates. These parity check sum value estimates are stored back into the memory (52), and after addition with the extrinsic estimates, are stored in a column sum memory (66) of a corresponding bit update circuit (60) as updated probability values for the input nodes.Type: ApplicationFiled: March 23, 2004Publication date: September 30, 2004Applicant: Texas Instruments IncorporatedInventor: Dale E. Hocevar
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Publication number: 20040191999Abstract: Fabricating a semiconductor includes forming a conductive layer outwardly from a surface of a substrate. A mask layer comprising a hard mask is deposited outwardly from the conductive layer to pattern the conductive layer to form a gate stack. The conductive layer is etched to remove the conductive layer from the surface of the substrate and to form the gate stack, where the mask layer is disposed outwardly from the gate stack. Ions are implanted outwardly from the surface of the substrate, where the mask layer prevents at least a portion of the ions from penetrating the gate stack while penetrating the substrate.Type: ApplicationFiled: March 24, 2003Publication date: September 30, 2004Applicant: Texas Instruments IncroporatedInventors: Pr Chidambaram, Srinivasan Chakravarthi, Gautam V. Thakar, Toan Tran
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Patent number: 6796023Abstract: While the manufacturing of integrated circuits (IC) has become a mostly automated process, the loading of the ICs into storage and shipping tubes 105 still requires a large amount of human interaction. A major stumbling block to the automation is the removal and insertion of retention pins 115 in the tubes. The present invention uses pressurized air 406 to hold a partially extracted retention pin 115 in position while the tube 105 is loaded. Once loaded, the retention pin 115 is reinserted. By not fully extracting the retention pin 115, alignment is maintained, simplifying the reinsertion step.Type: GrantFiled: July 8, 2002Date of Patent: September 28, 2004Assignee: Texas Instruments IncorporatedInventors: Jose Luis Estrada, Omar Carlin
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Patent number: 6799266Abstract: A method for reducing total code size in a processor having an exposed pipeline may include the steps of determining a latency between a load instruction, and a using instruction and inserting a NOP field into the defining or using instruction. When inserted into the load instruction, the NOP field defines the following latency following the load instruction. When inserted into the using instruction, the NOP field defines the latency preceding the using instruction. In addition, a method for reducing total code size during branching may include the steps of determining a latency following a branch instruction for initiating a branch from a first point to a second point in an instruction stream, and inserting a NOP field into the branch instruction.Type: GrantFiled: October 31, 2000Date of Patent: September 28, 2004Assignee: Texas Instruments IncorporatedInventors: Eric J. Stotzer, Elana D. Granston, Alan S. Ward
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Patent number: 6798521Abstract: A surface plasmon resonance (SPR) sensor (10) is disclosed. The sensor (10) includes a light source (18) and polarizer (20), which emit polarized light toward a surface plasmon layer (22). Light is reflected from the surface plasmon layer (22) at many angles, toward a photodetector array (26) via a mirror surface (24). The surface plasmon layer (22) includes a resonance film (30), such as gold, and a hard protective layer (32). The hard protective layer (32) is of a thickness below the sensing range (R) of the SPR sensor (10), and protects the resonance film (30) from damage. Materials useful as the hard protective layer (32) include silicon carbide (SiC), diamond-like carbon (DLC), silicon dioxide, silicon nitride, titanium oxide, titanium nitride, aluminum oxide, aluminum nitride, beryllium oxide, and tantalum oxide.Type: GrantFiled: October 25, 2001Date of Patent: September 28, 2004Assignee: Texas Instruments IncorporatedInventors: Jerome L. Elkind, Keren Deng
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Patent number: 6799136Abstract: A method for extracting blanket (qual) polish rates from interferometry signals off patterned (product) wafer polish during non-enpointed CMP. The method includes estimating polish rates using polish data near the end of the polish period. Non-linear regression and iterative optimization is presented to extract relevant information. The processing includes least square processing step (43), determining the search fit (44) and determining if this is the best fit (45).Type: GrantFiled: August 8, 2002Date of Patent: September 28, 2004Assignee: Texas Instruments IncorporatedInventors: Nital Patel, Gregory A. Miller, Steven T. Jenkins
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Patent number: 6798296Abstract: A wide band, wide operating range, general purpose digital phase locked loop (PLL) runs in the digital domain except for the associated Time Digitizer (T2D) and Digitally-Controlled-Oscillator (DCO). By calibrating the T2D and DCO on the fly, a constant PLL loop BW is achieved by using the calibrated Phase Frequency Detection (PFD) and DCO information to normalize the control loop correction regardless of the input clock frequency, power supply voltage, processing and temperature variations. PLL loop BW is completely decoupled from the operating conditions and semiconductor device variation. This means that the PLL loop BW can be chosen very aggressively to reject the noise, thus achieving a low jitter, high performance PLL. Furthermore, since this PLL can reliably operate over a wide operating range, it is a one-design-fits-all general purpose PLL.Type: GrantFiled: November 12, 2002Date of Patent: September 28, 2004Assignee: Texas Instruments IncorporatedInventors: Heng-Chih Lin, Baher S. Haroun, Tiang Tun Foo
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Patent number: 6799134Abstract: A method and circuit for verifying the burst-mode operation and the frequency characterization of a self-timed sequential circuit 2 in burst mode by detecting and measuring an output 15 of the self-timed sequential circuit 2.Type: GrantFiled: August 9, 2002Date of Patent: September 28, 2004Assignee: Texas Instruments IncorporatedInventors: Brian D. Borchers, Stephen W. Spriggs