Abstract: Disclosed herein is an improved optical interface system for a DMD array. One embodiment of the disclosed invention comprises an optical beam module that has an integral optical waveguide with waveguide ports at each end. The optical waveguide receives an input light beam through a first waveguide port. The input light beam passes through the waveguide and is emitted from the second waveguide port, where it is reflected by the reflective surface. The reflective surface can be integral to the optical beam module, or it can be mounted onto the module. After being reflected by the reflective surface, the input light beam can be directed onto the surface of a DMD array, where some or all of the input light beam can be selectively reflected in a particular direction. The reflective surface may also comprise a diffractive grating, which reflects the various wavelengths components of the input light beam at varying angles, thereby enabling wavelength selective switching.

Abstract: A piezo actuator drive circuit (40) adapted to operate in both a charge mode and a voltage mode. A low frequency compensation loop (44) is formed from a piezo actuator output (OUT6XP) of a driver (42) to the input thereof. The resulting closed loop system produces charge mode operation within a bandpass that can be tuned for desired operation. Below the bandpass turn on frequency (Fh) the closed loop system restores the piezo output (OUT6XP) to a defined DC voltage and compensates for any wandering effects, such as DC current mismatches in the closed loop configuration, such that the piezo output is centered around the desired DC operating point. The circuit is further provided with a DC restore feature in combination with the feedback which allows for a low frequency DC coupled path and thus allows for the DC positioning of the piezo in the charge mode to be changed. The DC restoring amplifier is used to compensate for offsets in the amplifier chain.

Abstract: Systems and methodologies are disclosed for interfacing a storage medium with a host using a segmented buffer. Data blocks are transferred between the host and medium according to logical block addresses, with buffer segment pointers indicating the logical block addresses of data blocks in the buffer. Buffer management hardware or firmware compares the pointer values directly with logical block addresses from host commands in order to determine whether desired data blocks are within the buffer.

Abstract: An improved sigma-delta modulation technique that may be employed in a sigma-delta Digital-to-Analog Converter (DAC) to convert digital signals into corresponding analog signals over a wide signal range and with high linearity. The sigma-delta DAC comprises a sigma-delta modulator including a variable quantizer and a quantizer controller, and an internal DAC. The sigma-delta modulator adaptively quantizes the digital input signal to a first number p of quantization levels. Next, the quantizer controller controls the variable quantizer to correlate the p quantization levels to the amplitude of the digital input signal, thereby generating a second number q of quantization levels. The internal DAC then receives the q quantization levels from the variable quantizer one group of p levels at a time, and produces an analog output signal therefrom that corresponds to the digital input signal.

Abstract: A system for data communication is disclosed that comprises a hybrid circuit (220) that receives a signal. A switched gain circuit (204) coupled to the hybrid circuit (220) receives the signal from the hybrid circuit (220). A receiver circuit (206) coupled to the switched gain circuit (204) receives the signal from the switched gain circuit (204). The switched gain circuit (204) adjusts the power of the signal transmitted to the receiver circuit (206). More specifically, the switched gain circuit (204) detects the power of the signal received from the hybrid circuit (220), and adjusts the power of the signal transmitted to the receiver circuit (206) based upon the power of the signal received from the hybrid circuit (220). A method for data communication is disclosed. A signal is received using a hybrid circuit (220). The signal is transmitted to a switched gain circuit (204) coupled to the hybrid circuit (220). The power of the signal is adjusted using the switched gain circuit (204).

Abstract: A combination electricals package (12, 32) particularly for use with fractional horsepower compressor motors for various appliances has a first recess formed in the package for receipt of a motor starter (14) and a second recess formed in the package for receipt of a run capacitor (16) potted therein and having capacitor leads (16a) connected to a capacitor lead connecting portion (20e, 20e′) of a connector (20, 20′) also having a motor pin connecting portion (20d) and a motor starter connecting portion (20b). The capacitor lead connecting portion in a preferred embodiment includes spaced apart parallel extending rails to accommodate capacitor lead misalignment. In a modified embodiment the capacitor lead connecting portion includes quick connect receptacles for conventional capacitor quick connect terminals. The connectors are formed so that the same connector can be used in two opposite orientations for left and right connectors.

Abstract: A method is provided for forming dual work function gate electrodes. A dielectric layer is provided outwardly of a substrate. A metal layer is formed outwardly of the dielectric layer. A silicon-germanium layer is formed outwardly of the metal layer. A first portion of the silicon-germanium layer is removed to expose a first portion of the metal layer, with a second portion of the silicon-germanium layer remaining over a second portion of the metal layer. A silicon-germanium metal compound layer is formed from the second portion of the silicon-germanium layer and the second portion of the metal layer. A first gate electrode comprising the first portion of the metal layer is formed. A second gate electrode comprising the silicon-germanium metal compound layer is formed.

Abstract: A method of reducing by-product deposition inside wafer processing equipment includes providing a chamber having a peripheral inner wall and placing a semiconductor wafer within the chamber. The method also includes placing a ring within the chamber proximate the peripheral inner wall and introducing a plurality of reactant gases into the chamber and reacting the gases. The method also includes introducing a heated gas into the chamber through the ring proximate the peripheral inner wall to increase the temperature of the peripheral inner wall.

Abstract: The present invention provides a capacitor 300, a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the capacitor 300 includes a first conductive plate 320 located over a semiconductor substrate 310, wherein the first conductive plate 320 has a second conductive plate 340 located thereover. The capacitor 300, in the same embodiment, further includes a dielectric layer 330 located between the first conductive plate 320 and the second conductive plate 340, wherein the dielectric layer 330 includes a Group 17 element.

Abstract: A microprocessor and a method of operating the microprocessor are provided in which a portion of the microprocessor is partitioned into a plurality of partitions. A sequence of instructions is executed within an instruction pipeline of the microprocessor. A block of instructions within the sequence of instructions is repetitively executed in response to a local repeat instruction. Either prior to executing the block of instructions, or during the first iteration of the loop, a determination is made that at least one of the plurality of partitions is not needed to execute the block of instructions. Operation of the at least one identified partition is inhibited during the repetitive execution of the block of instructions in order to reduce power dissipation.

Abstract: A charge pump circuit is configured for charging of parasitic capacitances associated with charge pump capacitors in a manner that minimizes voltage ripple. The charge pump circuit is suitably configured with an independent charging circuit configured for supplying the current needed to charge the parasitic capacitances, rather than utilizing the reservoir capacitor to supply the needed current. The independent charging circuit can be implemented with various configurations of charge pump circuits, such as single phase or dual phase charge pumps, and/or doubler, tripler or inverter configurations. The independent charging circuit includes a parasitic charging capacitor or other voltage source configured with one or more switch devices configured to facilitate charging of the parasitics during any phases of operation of the charge pump circuit.

Abstract: A heterojunction bipolar transistor (30) in a silicon-on-insulator (SOI) structure is disclosed. The transistor collector (28), heterojunction base region (20), and intrinsic emitter region (25) are formed in the thin film silicon layer (6) overlying the buried insulator layer (4). A base electrode (10) is formed of polysilicon, and has a polysilicon filament (10f) that extends over the edge of an insulator layer (8) to contact the silicon layer (6). After formation of insulator filaments (12) along the edges of the base electrode (10) and insulator layer (8), the thin film silicon layer (6) is etched through, exposing an edge. An angled ion implantation then implants the heterojunction species, for example germanium and carbon, into the exposed edge of the thin film silicon layer (6), which after anneal forms the heterojunction base region (20).

Abstract: Disclosed is a method of making a mold lock for bonding leadframe-to-plastic in an IC package. Steps include providing niches from opposing sides of the leadframe. The opposing niches are arranged such that an aperture and a mechanical key are formed within the leadframe material by the partial intersection of the niches. The key is encapsulated with mold compound to form a lock. An IC package mold lock in a leadframe is also disclosed, the lock having an aperture, a key, and mold compound encapsulating the key. Additionally, an IC package employing the leadframe-to-plastic lock is disclosed.

Abstract: In order to analyze the conditions leading to a stall or a wait state in a digital signal processing unit, READY signals, that are typically applied to the execution unit of a central processing unit, are applied to external conductors. The external conductors are applied to input terminals of a logic “AND” gate. The output terminals of the logic “AND” gate provided a logic “1” in a no-stall condition and a logic “0” in a stall condition. The output signals of the logic “AND” gate are stored in a memory unit and can be retrieved to determine when a stall condition occurred. The external conductors also apply the READY signal to a stall analyzer unit. The stall analyzer unit identifies the specific condition causing the stall condition by which external conductor has the logic “0” signal applied thereto. An indicia of this stall condition is stored in the memory unit.

Abstract: A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an insulating layer having a first surface, a second surface and a plurality of vias filled with metal. Said first surface having one of said metal layers attached to provide electrical ground potential, and having a plurality of electrically insulated openings for outside electrical contacts. An outermost insulating film protecting the exposed surface of said ground layer, said film having a plurality of openings filled with metal suitable for solder ball attachment. Said second surface having the other of said metal layers attached, portions thereof being configured as a plurality of electrical signal lines, further portions as a plurality of first electrical power lines, and further portions as a plurality of second electrical power lines, selected signal and power lines being in contact with said vias.

Abstract: The present invention provides an ultra linear, high speed operational amplifier output stage (100). The advantages of the operational amplifier output stage disclosed is significantly higher linearity for the same supply current, or equivalent linearity using a lower supply current. The present invention achieves this using an pre-driver sub-stage (122) having a plurality of translinear loops so that there is no net signal loss to the final sub-stage (123). The output of the disclosed operational amplifier output stage takes the form; &dgr;Io≈&bgr;n*&bgr;p*&dgr;Iin. When used with a localized feedback circuitry, bandwidth is extended.

Abstract: The present invention provides a semiconductor device 200 having a localized halo implant 250 located therein, a method of manufacture therefore and an integrated circuit including the semiconductor device. In one embodiment, the semiconductor device 200 includes a gate 244 located over a substrate 210, the substrate 210 having a source and a drain 230 located therein. In the same embodiment, located adjacent each of the source and drain 230 are localized halo implants 250, each of the localized halo implants 250 having a vertical implant region 260 and an angled implant region 265. Further, at an intersection of the vertical implant region 260 and the angled implant region 265 is an area of peak concentration.

Abstract: A pnp bipolar junction transistor is formed with improved emitter efficiency by reducing the depth of the p well implant to increase carrier concentration in the emitter and making the emitter junction deeper to increase minority lifetime in the emitter. The high gain BJT is formed without added mask steps to the process flow. A blanket high energy boron implant is used to suppress the isolation leakage in SRAM in the preferred embodiment.

Abstract: Methods of reducing contouring in images display by a linear display device, such as a spatial light modulator. The methods operate on a high resolution signal, which represents a stream of pixel values. The per pixel resolution of this signal is greater than the per pixel display resolution, and its less significant bits are treated as an error component. Random values are added to the error component either in conjunction with error diffusion values (FIG. 1) or to provide a dither that is directly proportional to the error (FIG. 4), or to provide a dither that has both spatial and temporal contributions (FIG. 5).

Abstract: The present invention provides an integrated circuit testing device 200 and a method of using the same. In one particular embodiment, the integrated circuit testing device may include a first circuit layer 220 located over a semiconductor substrate 210, wherein the first circuit layer 220 has a second circuit layer 230 located thereover. The integrated circuit testing device 200 of the same embodiment may further include a signal bond pad 240 selectively connectable to each of the first and second circuit layers 220, 230 to test at least one device on each of the first and second circuit layers 220, 230.