Abstract: A digital system has at least one processor, with an associated multi-segment cache memory circuit. A single global validity circuit (VIG) is connected to the memory circuit and is operable to indicate if any segment of the multiple segments holds valid data. Block circuitry is operable to transfer data from a pre-selected region of the secondary memory to a particular segment of the plurality of segments and to assert the global valid bit at the completion of a block transfer. Direct memory access (DMA) circuitry is connected to the memory cache for transferring data between the memory cache and a selectable region of a secondary memory and is also operable to assert the global valid bit at the completion of a DMA block transfer.

Abstract: A system and methodology for fabricating integrated circuits (ICs) on wafer die monitors at a subset of die one or more parameters that can affect the performance capabilities of associated ICs. One or more respective parameters for unmeasured die are derived based on one or more of the measured parameter. Fuses are selectively set for ICs at each die location based on parameters associated with each respective die location, thereby configuring the respective ICs accordingly.

Abstract: Methods for measuring and automatically controlling the light distribution and overall brightness in electronic-based spatial light modulator projection display systems. One method takes a small fraction of the projected light from a partial turning mirror 407 in the projector's optics path and focuses this light on to a detector 420 for use in controlling the light distribution and brightness of the system. Another method uses an array of embedded light sensors 518-522 at chosen locations on the surface of a display screen 517 to control the light distribution and brightness parameters of the projection system. Both methods use a micro-controller, servomotors, and an adjustable power supply, controlled by the detector/sensor outputs, to maintain the desired light distribution and brightness in the projected image.

Abstract: A variable-gain amplifier that prevents the change in the in-phase voltage of the output occurring when the gain is changed and improves the frequency characteristic compared with the conventional method. The differential current of currents I13 and I13′ changes corresponding to input signal S1. As a result, the differential current of currents I11 and I12 also change correspondingly, and the differential voltage v13 between nodes N1 and N2 varies. The gain of differential voltage v13 with respect to input signal S1 is variable corresponding to the current conversion gains of current converters 2 and 3. When the current conversion gains vary corresponding to the input signal S2, the voltages at nodes N1′ and N2′ are adjusted such that the voltages at nodes N1 and N2 are constant with respect to the change in gain.

Abstract: A Miller-compensated amplifier circuit. The circuit includes an amplifier stage, and a compensation capacitor arranged in parallel with the amplifier stage. A current multiplier circuit path, adapted to multiply a current through the compensation capacitor, includes an inversion stage in the current multiplier circuit path. The inversion stage includes a first current mirror adapted to mirror a first current corresponding to a current through the compensation capacitor, to provide a second current, as well as a second current mirror adapted to mirror and invert the second current to provide a third current and to apply the third current to the amplifier stage. In this way, the circuit is Miller compensated by only a single capacitor that has its capacitance multiplied in accordance with current-mode multiplication.

Abstract: Image enhancement is automatically achieved by calibrating the reference voltage and gain of a differential amplifier and the integration interval so as to provide an input to a differential analog to digital converter (ADC) that utilizes the full dynamic range of the ADC. When used with a CMOS array, the imaging logic can be fabricated on a single chip with the array using combinational logic for fast, inexpensive calibration. Another advantageous feature is the ability to expand a desired portion of the luminance spectrum of the image in order to increase the digital resolution of the resulting image for that portion of the spectrum of interest.

Abstract: The pixels of an image sensor array can be readout (84, 85) in m×n blocks (m, n) that are compatible with the operation of a desired image compression algorithm (14), thereby reducing the amount of memory required by the image compression algorithm.

Abstract: A processor (13) operates to determine amount of charge presently stored in a battery by determining that the battery is in a zero-current relaxed condition. Circuitry (16,23) including a first ADC (16) measures an open circuit voltage (OCV) of the battery prior to a period of time during which flow of current through the battery is not negligible. A program executed by the processor correlates the measured open circuit voltage (OCV0) with a corresponding value of the variable and selects the corresponding value as a value of the variable.

Abstract: A method is disclosed wherewith a person skilled in the art of statistical quality control may determine whether a process, a product or a service is statically equivalent to another of known quality, or to a desired known quality. The method may also be used to determine whether multiplicities of products, processes, or services are statistically equivalent to one another and of a desired quality. The method makes the determination based on an equivalency index that is derived from integration of the probability distribution of data of measurement taken from products processes, or services.

Abstract: An integrated circuit device with a low stress, thin film, protective overcoat having enhanced adhesion both to polymeric materials used in packaging-semiconductor devices, and within the passivating film layers, including the following sequence of materials deposited by PECVD processing: a thin film of silicon dioxide, a layer of silicon nitride, oxy-nitride or silicon carbide, and a very thin topmost layer of silicon oxide.

Abstract: The invention relates to a voltage-controlled oscillator circuit including an oscillator circuit connected to a voltage source furnishing a substantially constant supply voltage, and comprising at least one varactor, and a control voltage generator circuit whose output is connected to the anode of the varactor, the frequency of the oscillation signal of the oscillator circuit being variable by changing the control voltage. A voltage converter circuit and an ON/OFF switch therefor is located between the voltage source and the oscillator circuit, the conversion factor of the voltage converter circuit being selected so that a wide tuning range of the varactor and thus a wide frequency range of the oscillation signal is available. The invention can be put to use, for example, in a phase-locked loop. The oscillator circuit may be powered by a fixed predefined battery voltage.

Abstract: In a digital processing unit having a plurality of digital signal processors, a first digital signal processor can request a direct transfer of a signal group stored in the memory unit of a second digital signal processor. In order to insure that the second digital signal is active, a control signal is generated by the direct memory access controller of the first digital signal processor. The control signal is applied the directly to the memory access controller of the second digital signal processor. When the second digital signal processor is in an IDLE mode, the control signal activates the second digital signal processor.

Abstract: A method and apparatus for measuring the transient behavior characteristics of individual micromirrors in a DMD micromirror array. The method and system use sampling techniques to measure an amount of light reflected by an individual micromirror as the entire micromirror array is stimulated with a pattern of alternating driving signals. Sampling is achieved by illuminating the DMD micromirror array with a high-speed illumination source that provides stroboscopic light flashes of very short time length. By synchronizing the light flashes with the mirror driving signal and measuring the amount of light reflected by the individual micromirrors at different points in time, the transient behavior characteristics of individual micromirrors in a DMD micromirror array can be measured with a high level of accuracy.

Abstract: A method of fabricating a micromechanical device. Several of the micromechanical devices are fabricated 20 on a common wafer. After the devices are fabricated, the sacrificial layers are removed 22 leaving open spaces where the sacrificial layers once were. These open spaces allow for movement of the components of the micromechanical device. The devices optionally are passivated 24, which may include the application of a lubricant. After the devices have been passivated, they are tested 26 in wafer form. After testing 26, any surface treatments that are not compatible with the remainder of the processing steps are removed 28. The substrate wafer containing the completed devices receives a conformal overcoat 30. The overcoat layer is thick enough to project the micromechanical structures, but thin and light enough to prevent deforming the underlying micromechanical structures.

Abstract: A method of forming a via in an integrated circuit is provided. The method includes forming a stack including a first layer, a hard mask layer, and at least one intermediate layer disposed between the first layer and the hard mask layer. The first layer comprises a first metal line. The method further includes forming a channel in the hard mask layer. The channel has a first side and a second side opposite the first side. The method further includes forming a resist layer having an opening extending over both the first and second sides of the channel. The method further includes forming a metal line trench and a via opening aligned with the first and second sides of the channel. The method further includes filling the filling the metal line trench and the via opening with a conductive material to create a second metal line and a via connecting the second metal line with the first metal line.

Abstract: A method for measuring a capacitance of a semiconductor is provided that includes positioning a measurement circuit in a scribe line area associated with the semiconductor. The scribe line area is indicative of a delineation that separates one or more portions of the semiconductor. A capacitance of one or more elements included within the one or more portions of the semiconductor is then measured using the measurement circuit. The method also includes comparing the capacitance measurement of the one or more elements included within the one or more portions of the semiconductor to a reference set of capacitance values such that a parameter associated with a manufacturing process that generated the semiconductor may be checked.

Abstract: A method of preparing a TEM sample. A focused ion beam is used to deposit a mask on the material to be sampled. Reactive ion etching removes material not protected by the mask, leaving a wall thin enough to be imaged by TEM.

Abstract: A computerized system and method for inspecting and measuring a ball-shaped wire bond formed by an automated bonder pre-programmed to attach a connecting bond onto a bond pad of an integrated circuit by first obtaining a first image of said bond pad before bond attachment, then determining the coordinates of the center of said pad. Second, the bonder is instructed to attach a ball-shaped wire bond to the center of said pad. Next, a second image of said bond pad is obtained after bond attachment; this second image comprises an image of the ball-shaped portion of the bond and an image of the wire portion of said bond. The coordinates of the center of the ball-shaped portion of the bond are obtained by computer processing of the first and second images. The coordinates of the bond center and the pad center are compared, creating information for quality control of the bonder instruction and the bonding process.

Abstract: A system for fabricating a mixed voltage integrated circuit is disclosed in which a gate is provided that contains a gate oxide and a gate conductor on a substrate. A first mask is deposited to pattern the length of the gate by etching, and a second mask pattern is deposited and used to etch the width of the gate, with or without a hard mask.

Abstract: Methods are presented for fabricating MOS transistors, in which a sacrificial material such as silicon germanium is formed over a gate contact material prior to gate patterning. The sacrificial material is then removed following sidewall spacer formation to provide a recess at the top of the gate structure. The recess provides space for optional epitaxial silicon formation and suicide formation over the gate contact material without overflowing the tops of the sidewall spacers to minimize shorting between the gate and the source/drains in the finished transistor.