Abstract: A process for the manufacturing of integrated circuits provides for forming contacts between a conductive material layer and first doped regions of a semiconductor substrate in a self-aligned manner to edges of an insulating material layer which defines active areas of the integrated circuit wherein the doped regions are formed, and second doped regions of the same conductivity type as the first doped regions under the first doped regions, the second doped regions extending partially under the edges of the insulating material layer to prevent short-circuits between the conductive material layer and the semiconductor substrate. The second doped regions are formed by means of implantation of dopants along directions slanted with respect to an orthogonal direction to a surface of the semiconductor substrate at angles and with an energy sufficiently high to make the dopants penetrate in the semiconductor material deeper than the first doped regions and under the edges of the insulating material layer.

Abstract: A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material. The electronic circuit is of the type that calls for formation above the major surface of at least one dielectric multilayer. The dielectric multilayer includes a layer of amorphous planarizing material having a continuous portion extending between two contiguous areas with a more internal first area and a more external second area in the morphological structure. The device edge morphological structure includes in the substrate an excavation on the side of the major surface at the more internal first area of the morphological structure in a zone in which is present the continuous portion of the dielectric multilayer.

Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulating material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes a first elongated window in the conductive material layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a second insulating material layer disposed above the conductive material layer and disposed along elongated edges of the first elongated window.

Abstract: A monolithically integrated power device for driving electrical loads includes a power stage having a high-voltage bipolar transistor and a low-voltage auxiliary transistor cascade-connected and inserted between a first power supply terminal and a second power supply terminal of the device. The power device also includes a driver circuit for the power stage having an input connected to an input terminal of the device. In accordance with the present invention the device includes a circuit for protection thereof against an excessive temperature rise and controlling power down of the power stage.

Abstract: A MOS-gated power device integrated structure comprises a plurality of elementary units formed in a semiconductor material layer of a first conductivity type. Each elementary unit is formed in a body stripe of a second conductivity type. There are a plurality of body stripes of the second conductivity type extending substantially in parallel to each other and at least one source region of the first conductivity type disposed within each body stripe. A conductive gate layer is insulatively disposed over the semiconductor material layer between the body stripes in the form of a first web structure. A second web structure of the second conductivity type is formed in the semiconductor material layer and comprises an annular frame portion surrounding the plurality of body stripes and at least one first elongated stripe extending between two sides of the annular frame portion in a direction substantially orthogonal to the body stripes and that is merged at each end with the annular frame portion.

Abstract: A circuit for the generation of an electrical signal of constant duration comprises a capacitor, a constant current generator for charging the capacitor, and a voltage comparator to compare the voltage present at the terminals of the capacitor with a reference voltage. The voltage comparator supplies at an output a digital signal dependent upon the voltage across the capacitor. The constant current generator comprises a transistor biased with a voltage between gate and source obtained as the difference between the sum of two gate-source voltages of two transistors and a gate-source voltage of another transistor.

Abstract: A neural cellular network for implementing a so-called Chua's circuit, and comprising at least first, second and third cells having respective first and second input terminals and respective state terminals, the first and second input terminals being to receive a first and a second reference signal, respectively, and the first cell, and the second and third cells being of mutually different types.

Abstract: System for decoding code words in the EFM-PLUS and/or EFM format in which an enumeration block makes it possible to associate in a one-to-one manner with each of the code words a numerical value from a practically continuous set of numerical values. The numerical value, possibly summed with an offset value, by an address generator, addresses a read-only memory in which are stored information codes, each of which is associated, as decoded information, with one of the code words.

Abstract: The DMOS transistor includes an n drain region, a p body region which forms, with the drain region, a junction having at least one edge portion with a small radius of curvature, an n+ source region which delimits a channel in the body region, p+ body contact regions, a gate electrode, a source and body electrode, and a drain electrode. To prevent the "snap-back" phenomenon when the junction is reverse biased with the source, body and gate electrodes short-circuited, a p+ region is associated with each of the edge portions having a small radius of curvature and is arranged so as to be closer to the associated edge portion than any part of the source region.

Abstract: A voltage-regulator circuit with a low voltage drop uses a DMOS power transistor driven by a charge pump. The control circuit includes two feedback loops: a first feedback loop having a high gain and accuracy but low response speed, and a second feedback loop having a wide passband and fast response speed, but low gain.

Abstract: A circuit for switching between supply voltages and in particular for non-volatile flash memory devices and of the type comprising a first and a second circuit branch each incorporating a pair of transistors connected in series provides that at least one branch of the circuit be structured with a bridge circuit made up of P-channel MOS transistors. The bridge is made of a first and a second pairs of transistors connected between a first supply voltage reference and a common node. The first pair comprises transistors bigger than the transistors of the second pair while between the transistors making up the second pair is inserted a pair of resistors. Between the pair of resistors there is an interconnection node connected to a corresponding interconnection node between the transistors of the first pair.

Abstract: A CMOS output buffer circuit includes a final amplifier stage having a pull-up transistor and a pull-down transistor connected between a voltage supply and ground and having a common output node, and a control circuitry for driving the final amplifier stage including a first logic gate supplied with an input data signal, the first logic gate driving the pull-up transistor, a second logic gate supplied with said input data signal, the second logic gate driving the pull-down transistor. The pull-up transistor has a bulk electrode connected to a switchable bulk line; an auxiliary circuit is provided which as long as a voltage of the output node is not higher than said supply voltage keeps said switchable bulk line connected to the voltage supply. The first logic gate includes circuitry for transferring the voltage of the output node to said switchable bulk line when the voltage of the output node exceeds the supply voltage.

Abstract: An electronic device for performing convolution operations comprises shift registers for receiving binary input values representative of an original matrix, synapses for storing weights correlated with a mask matrix, and neurons for outputting a binary result dependent on the sum of the binary values weighted by the synapses. Each synapse has a conductance correlated with the weight stored and dependent upon the binary input value. Each neuron generates the binary result in dependence on the total conductance of the corresponding synapses.

Abstract: An integrated capacitance multiplier circuit utilizes a pair of field effect transistors, biased in a conducting state, as virtual resistances of a classic operational amplifier network for implementing a capacitance multiplier function. The two field effect transistors have different sizes from each other for attaining a given ON-resistance ratio. A biasing circuit provides independently adjustable biasing voltages for the two field effect transistors. At least one of the two biasing voltages produced by the biasing circuit can be made dependent on temperature according to a certain dependency law in order to exploit the capacitance multiplier circuit for temperature compensating an integrated RC circuit employing the virtual capacitance provided by the multiplier circuit.

Abstract: Saturation of a bipolar power transistor is controlled by sensing the current which is eventually injected into the substrate of the integrated circuit by the saturating transistor and using this signal for exerting a limiting action on the current which is driven to the base of the power transistor by a dedicated driving circuit. Unlike the prior art antisaturation systems, it is no longer necessary to precisely monitor the operating voltages across the terminals of the bipolar power transistor. A suitable sensing resistance may be integrated conveniently at a distance from the often complex integrated structure of the bipolar transistor. The system of the invention offers numerous advantages and ensures intervention of the antisaturation circuit only when the power transistor has positively reached a state of saturation, but well before any unwanted consequence.

Abstract: The microtips of charge emitting material, which define the cathode of the flat FED screen and face the grid of the screen, are tubular and have portions with a small radius of curvature. The microtips are obtained by forming openings in the dielectric layer separating the cathode connection layer from the grid layer, depositing a conducting material layer to cover the walls of the openings, and anisotropically etching the layer of conducting material to form inwardly-inclined surfaces with emitting tips. Subsequently, the portions of the dielectric layer surrounding the microtips are removed.

Abstract: A filter performs a reduction of pulsed noise in video images in accordance with fuzzy logic. An interface circuit of the filter receives consecutive digital signals in time corresponding to the video images and generates an image window having a digital signal to be processed at the center. The filter also has a comparator block, a plurality of digital subtractors, and a memory circuit connected in cascade to the comparator block. The filter also has a filtering circuit that organizes values of digital signals of the video image, and an arithmetic block that performs a switch between the digital signal to be processed and the output of the filtering circuit on the basis of the values taken by the parameter.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulating material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes a first elongated window in the conductive material layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a second insulating material layer disposed above the conductive material layer and disposed along elongated edges of the first elongated window.

Abstract: A sense circuit for reading EPROM and ROM type memory cells employs a circuit for generating an offsetting current which is exempt of error during transients and which thus permits to achieve a reduced access time. On the other hand, the sense circuit maintains the intrinsic advantages of a current-offset sensing architecture which is represented by a substantially unlimited operating voltage range toward the maximum value VCC.sub.max. The current generating circuit is driven by means of a supplementary row of cells which is decoded at every reading and which replicates, during transients, the behaviour of the row selected for the reading.