Patents Assigned to Thomson Microelectronics S. R. L.
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Patent number: 6232140Abstract: The acceleration sensor is formed in a monocrystalline silicon wafer forming part of a dedicated SOI substrate presenting a first and second monocrystalline silicon wafer separated by an insulting layer having an air gap. A well is formed in the second wafer over the air gap and is subsequently trenched up to the air gap to release the monocrystalline silicon mass forming the movable mass of the sensor; the movable mass has two numbers of movable electrodes facing respective pluralities of fixed electrodes. In the idle condition, each movable electrode is separated by different distances from the two fixed electrodes facing the movable electrode.Type: GrantFiled: December 10, 1999Date of Patent: May 15, 2001Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Paolo Ferrari, Mario Foroni, Benedetto Vigna, Flavio Villa
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Patent number: 6230308Abstract: The method relates to assembling modules for an integrated circuit comprising at least a plurality of modules. The method provides for the formation of at least one module architecture which comprises a plurality of modules and is aligned along one dimension of such modules. The invention also concerns an integrated circuit and a stacked module architecture obtained with the inventive assembling method.Type: GrantFiled: March 23, 1998Date of Patent: May 8, 2001Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Roberto Ganzelmi, Cesare Pozzi, Alberto Battaia
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Patent number: 6222414Abstract: An output power stage which includes a PNP pull-up transistor and an n-channel FET push-down transistor, driven in phase opposition. This fully complementary stage provides an outstandingly improved power handling capability per semiconductor area occupied, together with a large output voltage swing, but does not require the use of externally connected discrete boot-strap components. The bipolar pull-up transistor can optionally be driven through an FET auxiliary stage, to minimize the power requirements of the preceding signal amplification stage.Type: GrantFiled: December 7, 1994Date of Patent: April 24, 2001Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Carlo Cini, Fabrizio Stefani
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Patent number: 6222232Abstract: A MOS technology power device comprises a semiconductor substrate, a semiconductor layer of a first conductivity type superimposed over the semiconductor substrate, an insulated gate layer covering the semiconductor layer, a plurality of substantially rectilinear elongated openings parallel to each other in the insulated gate layer, a respective plurality of elongated body stripes of a second conductivity type formed in the semiconductor layer under the elongated openings, source regions of the first conductivity type included in the body stripes and a metal layer covering the insulated gate layer and contacting the body stripes and the source regions through the elongated openings.Type: GrantFiled: July 1, 1997Date of Patent: April 24, 2001Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Angelo Magri', Raffaele Zambrano, Ferruccio Frisina
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Patent number: 6222245Abstract: The invention relates to a high-capacitance capacitor which is monolithically integratable on a semiconductor substrate doped with a first type of dopant and accommodating a diffusion well which is doped with a second type of dopant and has a first active region formed therein. A layer of gate oxide is deposited over the diffusion well which is covered with a first layer of polycrystalline silicon and separated from a second layer of polycrystalline silicon by an interpoly dielectric layer. Advantageously, the high-capacitance capacitor of the invention includes a first elementary capacitor having the first and second layers of polycrystalline silicon as its conductive plates, and the interpoly dielectric layer as the isolation dielectric, and a second elementary capacitor having the first layer of polycrystalline silicon and the diffusion well as its conductive plates and the gate oxide layer as the isolation dielectric.Type: GrantFiled: October 30, 1996Date of Patent: April 24, 2001Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Roberto Bez, Emilio Camerlenghi
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Patent number: 6215329Abstract: The present invention relates to an output stage for an electronic memory device and for low supply-voltage applications and is the type comprising a final stage of the pull-up/pull-down type made up of a complementary pair of transistors inserted between a primary reference supply voltage and a secondary reference voltage and a voltage regulator for the control terminals of said transistors. The regulator is a voltage booster using at least one bootstrap capacitor to increase the current flowing in the final stage by boosting the voltage applied to said control terminals.Type: GrantFiled: July 23, 1997Date of Patent: April 10, 2001Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Giovanni Campardo, Stefano Zanardi, Andrea Ghilardelli
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Patent number: 6212287Abstract: A method, in a system for aiding the guidance of a vehicle, for identifying marking stripes of road lanes. A road image is subjected to a convolution operation with a mask matrix so as to identify discontinuities present in the image. The resulting convolved image is compared with a threshold value and a representation of the marking stripes is determined. The mask matrix is set in such a way as to eliminate at least partially the discontinuities which do not correspond to the marking stripes.Type: GrantFiled: October 17, 1997Date of Patent: April 3, 2001Assignee: SGS-Thomson Microelectronics S.R.L.Inventors: Massimiliano Olivieri, Vito Fabbrizio, Roberto Guerrieri, Alan Kramer
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Patent number: 6211705Abstract: A timed bistable circuit is described which includes two inverters each having its input connected to the output of the other, an output of the circuit via a “buffer” and an input of the circuit via a controlled electronic switch. The supply terminals of the inverters are connected to the supply terminals of the circuit via another two controlled switches. A clock generator provides timing signals to control both the input switches to open or close and to control the supply switches to close or open when the input switches are open or closed respectively. To obtain a latch usable in a comparator at a high comparison frequency the offset referred to the input is reduced and made independent of the frequency by arranging two further electronic switches between the supply terminals of the inverters and the supply terminals which are controlled by a timing signal in such a way as to close with a predetermined delay with respect to the closure of the input switches and to open when input switches open.Type: GrantFiled: September 2, 1998Date of Patent: April 3, 2001Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Melchiorre Bruccoleri, Paolo Cusinato
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Patent number: 6212096Abstract: A data reading path management architecture for a memory device, particularly of the non-volatile type, comprising a memory matrix and data sensing means that are adapted to receive the data of the memory matrix for reading, which has the particularity that the memory matrix is divided into at least two half-matrices. Each one of the two half-matrices has a reference line that is adapted to constitute a reference for reading the other half-matrix. The data sensing means receive the data from one half-matrix and the reference from the other half-matrix and are adapted to transmit, according to a control timing, the data on an internal bus.Type: GrantFiled: July 12, 1999Date of Patent: April 3, 2001Assignee: SGS-Thomson Microelectronics S.r.l.Inventor: Luigi Pascucci
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Patent number: 6188121Abstract: A high voltage capacitor, integratable monolithically on a semiconductor substrate which accommodates a field oxide region overlaid by a first layer of polycrystalline silicon isolated from a second layer of polycrystalline silicon by an interpoly dielectric layer, comprises two elementary capacitors having a first common conductive plate which is formed in the first layer of polycrystalline silicon. Each of these elementary capacitors has a second conductive plate formed in the second layer of polycrystalline silicon above the first plate, and includes said interpoly dielectric layer as an isolation dielectric between the two plates.Type: GrantFiled: July 20, 1998Date of Patent: February 13, 2001Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Livio Baldi, Paolo Ghezzi, Alfonso Maurelli
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Patent number: 6187683Abstract: A planarization method is disclosed to provide improved protection against cracking of the final passivation layer of integrated circuit devices. In one embodiment, such method includes final passivation of an integrated circuit device including at least one integrated circuit chip. Such final passivation includes the step of forming a layer of protective material over a top surface of the integrated circuit chip, and a subsequent step of planarizing such layer of protective material to obtain a protection layer having a substantially flat top surface.Type: GrantFiled: April 14, 1998Date of Patent: February 13, 2001Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Giorgio De Santi, Luca Zanotti, Giuseppe Crisenza
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Patent number: 6188998Abstract: In a method, according to the invention, of storing one or more natural membership functions of respectively one or more natural variables being each defined within a natural universe of discourse having a lowest natural value and a highest natural value, the natural membership functions are normalized through respective normalization coefficients so that they are defined within the same predetermined absolute universe of discourse having a lowest absolute value and a highest absolute value, thereby obtaining one or more absolute membership functions, respectively, and said absolute membership functions and said normalization coefficients are stored, taking account that identical absolute membership functions are stored only once.Type: GrantFiled: February 26, 1997Date of Patent: February 13, 2001Assignees: SGS-Thomson Microelectronics S.r.l., Consorzio per la Ricerca sulla Microelettronica nel MezzogiornoInventors: Antonino Cuce', Matteo Lo Presti
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Patent number: 6184741Abstract: A charge pump comprises at least one charge pump stage including a first diode having an anode and a cathode, and a capacitor having a first plate connected to the cathode of the diode and a second plate connected to a clock signal that periodically varies between a reference voltage and a supply voltage, the anode of said diode forming a first terminal of the charge pump. The charge pump further comprises a second diode having an anode connected to the cathode of the first diode and a cathode forming a second terminal of the charge pump, first switching means for selectively coupling the first terminal of the charge pump to the voltage supply and second switching means for selectively coupling the second terminal of the charge pump to the reference voltage.Type: GrantFiled: July 28, 1997Date of Patent: February 6, 2001Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Andrea Ghilardelli, Giovanni Campardo, Jacopo Mulatti
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Patent number: 6175521Abstract: A voltage regulator for programming electrically programmable non-volatile memory cells in a cell matrix that is divided in segments. The voltage regulator includes an amplifier stage connected and powered between a first reference voltage and a second reference voltage and having a first input terminal connected to a voltage divider of the first reference voltage, an output terminal connected to the control terminal of a MOS transistor which has a conduction terminal connected to the memory cells through a programming line, and a second input terminal connected to the programming line, and connected to the output terminal in a feedback loop. The voltage regulator includes an input circuit portion made up of active elements and inserted in turn between the first and second reference voltages.Type: GrantFiled: April 4, 1997Date of Patent: January 16, 2001Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Luigi Pascucci, Marco Fontana
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Patent number: 6175657Abstract: The level of Gaussian noise in a memory field being scanned by rows is reduced by reconstructing each pixel by fuzzy logic processors. The processors process the values of pixels neighboring the pixel being processed and belonging to a processing window defined by the last scanned row and the row being scanned, thus minimizing the memory requirement of the filtering system to a single row. The system performs an adaptive filtering within the current field itself and does not produce “edge-smoothing” effects as in prior adaptive filtering systems operating on consecutive fields.Type: GrantFiled: May 7, 1998Date of Patent: January 16, 2001Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Massimo Mancuso, Viviana D'Alto, Daniele Sirtori, Rinaldo Poluzzi
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Patent number: 6171931Abstract: A wafer of semiconductor material for fabricating integrated devices, including a stack of superimposed layers including first and second monocrystalline silicon layers separated by an intermediate insulating layer made of a material selected from the group comprising silicon carbide, silicon nitride and ceramic materials. An oxide bond layer is provided between the intermediate layer and the second silicon layer. The wafer is fabricated by forming the intermediate insulating layer on the first silicon layer in a heated vacuum chamber; depositing the oxide layer; and superimposing the second silicon layer. When the stack of silicon, insulating material, oxide and silicon layers is heat treated, the oxide reacts so as to bond the insulating layer to the second silicon layer. As a ceramic material beryllium oxide, aluminium nitride, boron nitride and alumina may be used.Type: GrantFiled: October 6, 1998Date of Patent: January 9, 2001Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Bruno Murari, Flavio Villa, Ubaldo Mastromatteo
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Patent number: 6169300Abstract: An Insulated Gate Bipolar Transistor includes a semiconductor substrate of a first conductivity type forming a first electrode of the device, a semiconductor layer of a second conductivity type superimposed over said substrate, a plurality of body regions of the first conductivity type formed in the semiconductor layer, a first doped region of the second conductivity type formed inside each body region, an insulated gate layer superimposed over portions of the semiconductor layer between the body regions and forming a control electrode of the device, a conductive layer insulatively disposed over the insulated gate layer and contacting each body region and each doped region formed therein, the conductive layer forming a second electrode of the device.Type: GrantFiled: March 4, 1998Date of Patent: January 2, 2001Assignee: SGS-Thomson Microelectronics S.r.l.Inventor: Leonardo Fragapane
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Patent number: 6154163Abstract: A successive approximation register has a serial input and output comprises a chain of logic circuits of the bistable type which have selectable input terminals feedback connected by a storage and control element and logic gate circuits of the OR-type, and connected to a serial line through respective internal switches communicating the serial line to input terminals of the logic circuits in said chain, the serial line forming an input to a flip-flop of the D type which is the output element of the register.Type: GrantFiled: June 29, 1998Date of Patent: November 28, 2000Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Annamaria Rossi, Giona Fucili, Marcello Leone, Maurizio Nessi
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Patent number: 6153537Abstract: A method for manufacturing a semiconductor device having improved adhesion at an interface between layers of dielectric material, comprising the steps of forming a first layer of dielectric material on at least one part of a structure defined in a semiconductor substrate and forming a second dielectric material layer superimposed on the least one part of the first layer. The method further includes the step of forming, in the part where the first and second layers are superimposed, an intermediate adhesion layer comprising a ternary compound of silicon, oxygen and carbon. The formation of the adhesion layer takes place at low temperature and in an atmosphere kept essentially free of oxidative substances different from those serving to provide the silicon and the carbon to the layer. Preferably the layer is formed by the plasma enhanced chemical vapour deposition technique.Type: GrantFiled: December 22, 1995Date of Patent: November 28, 2000Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Maurizio Bacchetta, Luca Zanotti, Giuseppe Queirolo
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Patent number: 6150853Abstract: The operation of externally connected output power transistors of a class AB amplifier is controlled without employing any external sensing resistance of the output current by driving an externally connected power transistor through a level shifting buffer and employing a limiting network composed of an integrated transistor driven by the output of a signal amplifying stage and a resistance connected in series with its drain. The buffer stage shifts the level of the driving signal of the external power transistor by a value equal to the threshold voltage of the integrated transistor of the limiting network thus ensuring the turn-off of the external power transistor under quiescent conditions.Type: GrantFiled: February 27, 1995Date of Patent: November 21, 2000Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Francesco Chrappan, Maurizio Nessi, Alberto Salina