Abstract: A memory cell for devices of the EEPROM type, formed in a portion of a semiconductor material substrate having a first conductivity type. The memory cell includes source and drain regions having a second conductivity type and extending at the sides of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region, and a channel region extending between the region of electric continuity and the source region. The memory cell further includes an implanted region having the first conductivity type and being formed laterally and beneath the gate oxide region and incorporating the channel region.

Abstract: The ratio y(n) of two digital values, respectively a(n) and b(n), representing the n.sup.th elements of two respective sequences of digital input data representing two quantities slowly varying in time, is obtained by computingy(n)=y(n-1)+g*[a(n)-b(n)*y(n-1)]wherein g represents a multiplying factor. Within the domain of the z transform, the expression becomes:Y(z)=z.sup.-1 *Y(z)+g[A(z)-B(z)conv Y(z)*z.sup.-1where conv indicates an operation of convolution and which, for input sequences corresponding to signals filtered through a lowpass filter with a time constant greater than or equal to 3 msec is simplified to: ##EQU1## The approximation is exceptionally good and computation thereof may be achieved by the use of relatively simple hardware, without severely burdening the workload of a microprocessor.

Abstract: An insulating film between stacked electrically conducting layers through which interconnections of integrated circuits are realized, is formed of an aerogel of an inorganic oxide on which organic monomers have been grafted under inert ion bombardment and successively further incorporated in the aerogel to fill at least partially the porosities of the inorganic aerogel. The composite dielectric material is thermally stable and has a satisfactory thermal budget. The method of forming an aerogel film includes the spinning of a precursor compound solution onto the wafer followed by supercritical solvent extraction carried out in the spinning chamber.

Abstract: A self-protected, low emission electronic device for driving a warning horn includes a coil powered from a battery through a control push-button adapted for operation by a user and included in an electric connection between a terminal of the coil and the battery. The device includes a protective circuit portion connected between the battery and the warning horn. The protective circuit portion includes a bridge structure of power components. At least a pair of the power components are MOS power transistors of which one is driven by a charge pump.

Abstract: A memory cell of the EEPROM type formed on a semiconductor material substrate having a first conductivity type includes a drain region having a second conductivity type and extending at one side of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region. The region of electric continuity is produced by implantation at a predetermined angle of inclination.

Abstract: A gain modulated sense amplifier, particularly for memory devices, that comprises a virtual ground latch structure which has two output nodes and which includes equalization transistor of a first polarity which equalizes the two output nodes and is connected between a first branch and a second branch, in which the output nodes are arranged; the equalization transistor is driven by an equalization signal whose slope can be modulated as a function of conductivity of a memory cell of the memory device.

Abstract: A voltage regulator of the type comprising a linear filter, a comparator, and a stretcher filter which are connected in cascade with one another between an input terminal and an output terminal of the regulator. The input terminal receives an error signal as converted by the comparator into a square-wave error signal, and the output terminal deliveres a square-wave output control signal which has a stretched duty cycle over the square-wave error signal by a time delay introduced from the stretcher filter. The regulator further comprises a non-linear filtering section for the error signal which is connected between the input terminal of the regulator and the linear filter and has linear gain with the error signal below a first value, gain approximately of unity with the error signal between the first value and a second value, and zero gain with the error signal above the second value.

Abstract: Driving of a three-phase motor includes controlling the slip of the motor by way of a fuzzy logic algorithm. The simplicity and precision of the fuzzy control of the slip permits dynamically optimizing the efficiency of a three-phase motor under any operating condition, and thereby minimizing power consumption. The control is carried out by knowing: the effective speed of the motor that represents the feedback value, and that may be provided by a common encoder (typically a dynamo or an optic device) keyed on the motor's spindled; the stator frequency imposed on the motor; the required speed; and, of course, the characteristic curve (frequency-torque) of the motor.

Abstract: A charge pump comprises a plurality of stages connected in series, an input terminal of the charge pump being connected to a voltage supply and an output terminal of the charge pump providing an output voltage higher than the voltage supply. Each stage comprises unidirectional current flow MOS transistor means connected between a stage input terminal and a stage output terminal allowing current to flow only from said stage input terminal to said stage output terminal, and a first capacitor with one plate connected to said stage output terminal and another plate driven by a respective first digital signal periodically switching between ground and said voltage supply.

Abstract: Cost-efficient integration of a fully-featured EEPROM memory block in a FLASH-EPROM memory device, fabricated according to a low supply voltage and low power consumption FLASH-EPROM process, is made possible by a special structure of the EEPROM cells whereby the capacitive coupling between the floating gate and the control gate of the cell is realized over the field oxide adjacent to the active area of the cell. The process of the invention permits an optimized modulation of the thicknesses of the different tunnel and gate oxides of the FLASH-EPROM and EEPROM cells, as well as of the transistors of the peripheral circuitry of the two memory blocks destined to work with a relatively low supply voltage or with a boosted voltage.

Abstract: A suspension arm (125) for a head (120) of a disk storage device comprises at least one wall (225, 230) substantially perpendicular to the disk (105) and having a portion (238, 239) which is deformable parallel to a plane extending through a longitudinal axis (235) of the suspension arm (125) and perpendicular to the at least one wall (225, 230), and piezoelectric member (240, 255) which can deform the portion (238, 239) in order correspondingly to move the head (120), the piezoelectric member (240-255) being fixed to the portion (238, 239) of the at least one wall (225, 230).

Abstract: A current generator circuit with controllable frequency response has at least one current mirror formed of MOS transistors, being powered through a terminal held at a constant voltage, having an input leg through which a reference current (I1) is driven by a first current generator (G1), and having an output leg for generating, on an output terminal (OUT) of the mirror, a mirrored current (I.sub.out) which is proportional to the reference current (I1). The input leg includes at least a first transistor (M1) which is diode-connected and has a control terminal (Ga1) coupled to a corresponding terminal (Ga2) of a second transistor (M2) included in the output leg. In accordance with the invention, the mirror circuit also has an impedance matching circuit connected across the control terminals (Ga1 and Ga2) of the first and second transistors and configured to hold the same voltage value at both terminals (Ga1 and Ga2).

Abstract: An anti-tampering circuit for a vehicle includes an operational circuit providing a predetermined function for the vehicle to be protected, and a control circuit connected to the operational circuit for enabling and disabling operation thereof. The control circuit includes a semiconductor substrate, a communications circuit formed on the semiconductor substrate receiving data corresponding to an identification code from at least one external source within the vehicle, and a non-volatile memory formed on the semiconductor substrate and connected to the communications circuit for storing only once a predetermined identification code. The communications circuit writes the received data to the non-volatile memory as the predetermined identification code when the control circuit is within the vehicle if the predetermined identification code has not already been stored therein.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided.

Abstract: A method is provided of manufacturing a P-channel native MOS transistor in a circuit integrated on a semiconductor which also includes a matrix of non-volatile memory cells of the floating gate type with two polysilicon levels having an interpoly dielectric layer sandwiched between the two polysilicon levels. The method has the following steps: (1) masking and defining active areas of the discrete integrated devices; (2) masking and defining the first polysilicon level using a Poly1 mask; and (3) masking and defining an intermediate dielectric layer using a matrix mask. The length of the native threshold channel of the native transistor is defined by means of the matrix mask and by etching away the interpoly dielectric layer.

Abstract: A CMOS output stage for providing stable quiescent current. The output stage includes a circuit that relates the quiescent current to the channel geometry of a power NMOS transistor and of an NMOS reference transistor of a reference current source. This configuration removes the dependency of the quiescent current on a power PMOS transistor used in the CMOS output stage, the threshold voltage of which may drift over time under high current and voltage operation, and adversely affects quiescent current stability.

Abstract: A low-noise output stage for an electronic circuit integrated on a semiconductor substrate is disclosed. The low-noise output stage comprises a complementary CMOS transistor pair including a P-channel pull-up transistor and an N-channel pull-down transistor, connected across a first terminal of the electronic circuit to receive a supply voltage, and a second terminal of the electronic circuit to receive a second reference potential. The transistors are connected together to form an output terminal of the electronic circuit for connection to an external load. The pull-down transistor is formed in a three-well structure to prevent propagation of a discharge current from the external load through the semiconductor substrate.

Abstract: The invention relates to a modular architecture of a cellular network for improved large-scale integration, of the type which comprises a plurality of fuzzy cellular elements (C.sub.m,n) interconnected to form a matrix of elements having at least m rows and n columns, the row and column numbers describing the location of each element. Each fuzzy processor is adapted for connection to other processors of the same type such that a parallel architecture of the modular type can be implemented. The management of the architecture is facilitated by each submatrix being controlled by an individually dedicated fuzzy processor device.

Abstract: A pre-charge step determining circuit of a generic bit line, particularly for non-volatile memories, including in one embodiment, circuitry for simulating the selection/deselection of a generic bit line of a memory device; circuitry for simulating the pre-charging of a bit line; and circuitry for determining when the working point of the bit line is reached; the selection/deselection simulation circuitry activating the pre-charging simulation means, which in turn activate the working point attainment determining circuitry, which generate a pre-charge end signal so as to define a minimal duration of the pre-charging that is closely correlated with the characteristics of the actual selection/deselection and pre-charge circuits of the memory device, with the supply conditions, and with the propagation of a generic bit line, the pre-charge simulation circuitry and the working point attainment determining circuitry being activated synchronously with respect to a new reading cycle of the memory device.

Abstract: A suppression method is applied to an integrated circuit formed on a substrate of p-type material having at least one region of n-type material with junction isolation, a first electrical contact on the frontal surface of the substrate, a second electrical contact on the n-type region and a third electrical contact on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact is taken to the potential of the second contact, otherwise they are held at the (ground) potential of the reference terminal. A device and an integrated circuit which utilize the method are also described.