Patents Assigned to Toshiba Ceramics Co., Ltd.
  • Publication number: 20070240628
    Abstract: Provided is a silicon wafer suitable for manufacturing a semiconductor device having a shallow junction. A silicon wafer wherein, in a region at a depth of less than 50 ?m from a surface, a density of oxygen deposition materials each having a diameter of not less than 10 nm is not more than 1×108/cm3. A silicon wafer for a semiconductor device, which is manufactured by applying heat treatment at a heat treatment temperature of not less than 1000° C. for heat treatment time of not more than 3 msec, wherein, in a region at a depth of less than 50 ?m from a surface, a density of oxygen deposition materials each having a diameter of not less than 10 nm is not more than 1×108/cm3.
    Type: Application
    Filed: April 5, 2007
    Publication date: October 18, 2007
    Applicant: Toshiba Ceramics Co., Ltd
    Inventors: Takashi Watanabe, Hiroyuki Saito, Takeshi Senda, Koji Izunome, Kazuhiko Kashima
  • Patent number: 7276125
    Abstract: The barrel type susceptor for use in the semiconductor epitaxial growth is characterized in that a face plate 5 of a susceptor main body 2 having the shape of a truncated cone is partitioned into two or more in a longitudinal direction thereof, each partition being provided with a wafer mounting concave portion 6a, 6b, 6c on which a wafer is laid, and the inclination angle ?a, ?b, ?c of a bottom face 6a1, 6b1, 6c1 of the concave portion for each partition to the vertical line is gradually decreased in each partition from the upper part to the lower part.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: October 2, 2007
    Assignees: Toshiba Ceramics Co., Ltd., Tokuyama Toshiba Ceramics Co., Ltd.
    Inventors: Toshikazu Miyamoto, Tadashi Ohashi
  • Publication number: 20070222977
    Abstract: A surface inspection apparatus, for inspecting a plurality of surfaces formed in a peripheral edge portion of a plate-like object, includes a image pickup mechanism, which photographs the peripheral edge portion of the plate-like object having a plurality of surfaces, and an image processing device, which processes an image obtained by the photographing device. The image pickup mechanism includes an optical system which guides images of the plurality of surfaces of the plate-like object in one direction, and a camera unit having an image pickup surface, on which the images of the plurality of surfaces guided by the optical system in the one direction are formed.
    Type: Application
    Filed: May 29, 2007
    Publication date: September 27, 2007
    Applicants: SHIBAURA MECHATRONICS CORPORATION, TOSHIBA CERAMICS CO., LTD.
    Inventors: Yoshinori Hayashi, Hiroyuki Naraidate, Makoto Kyoya, Koji Izunome, Hiromi Nagahama, Miyuki Shimizu, Kazuhiko Hamatani
  • Patent number: 7255775
    Abstract: There is provided a semiconductor wafer treatment member in which the occurrence of slippage thereof is prevented and which has an adequate cohesiveness onto the semiconductor wafer and an excellent durability. The semiconductor wafer treatment member A of the present invention has at least a surface formed with a silicon carbide (SiC) film thereon, comprising a support portion for receiving a semiconductor wafer, said support portion being composed of salients with which said semiconductor wafer substantially comes into contact; and depressions formed with the silicon carbide (SiC) film to provide a coverage area between said salients, said salients being formed with top surfaces having a surface roughness Ra of 0.05 ?m to 1.3 ?m.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: August 14, 2007
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Masanari Yokogawa, Hirotaka Hagihara, Shinya Wagatsuma, Koutarou Kitayama, Chieko Fujiwara
  • Patent number: 7250357
    Abstract: A manufacturing method for producing a stained silicon wafer has the steps of forming an Si1-xGex composition-graded layer of which Ge concentration is stepwisely increased on a single crystal silicon substrate, forming an Si1-xGex uniform composition layer of which Ge concentration is constant on the Si1-xGex composition-graded layer, forming a stain-relaxed Si1-yGey layer of which Ge concentration y is constant while y satisfies relationship of 0.5x?y<x on the Si1-xGex uniform composition layer and epitaxially growing a strained Si layer on the strain-relaxed Si1-yGey layer.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: July 31, 2007
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Takeshi Senda, Koji Izunome
  • Patent number: 7247583
    Abstract: A method for manufacturing a strained silicon wafer, having steps of a first step of preparing a single crystal silicon substrate, a second step of forming a graded SiGe layer on the substrate, the graded SiGe layer having a first Ge composition ratio increased stepwisely from 5 to 60% at atomic ratio, a third step of forming a SiGe constant composition layer on the graded SiGe layer, the SiGe constant composition layer having a Ge composition ratio substantially equal to the Ge composition ratio on a surface of the-graded SiGe layer and a fourth step of forming a strained Si layer on the SiGe constant composition layer. The second through fourth steps are performed under the reduced pressure atmosphere while the single crystal silicon substrate is rotated in a circumferential direction at a rate from 300 rpm to 1500 rpm.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: July 24, 2007
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Hisatsugu Kurita, Masato Igarashi, Takeshi Senda, Koji Izunome
  • Patent number: 7226513
    Abstract: This invention provides a cleaning method of silicon wafer for obtaining a silicon wafer in which micro roughness thereof under spatial frequency of 20/?m is 0.3 to 1.5 nm3 in terms of power spectrum density, by passing a process of oxidizing the silicon wafer with ozonized water and a process of cleaning said oxidized silicon wafer with hydrofluoric acid. Consequently, it is possible to remove surface adhering pollutant such as particles and metallic foreign matter with the surface structure of silicon wafer flattened up to atomic level by annealing maintained.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: June 5, 2007
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Hisatsugu Kurita, Manabu Hirasawa, Hiromi Nagahama, Koji Izumome, Takao Ino, Jyunsei Yamabe, Naoya Hayamizu, Naoaki Sakurai
  • Patent number: 7193294
    Abstract: A semiconductor substrate includes a support substrate 1 has gettering sites 10 for gettering impurity metal, an embedded insulating film 2 which is provided on the support substrate 1 and contains oxides of an element whose single bond energy to oxygen is higher than that to silicon, and a semiconductor layer (an SOI layer) 3 provided on the embedded insulating film 2.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: March 20, 2007
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Reiko Yoshimura, Tsukasa Tada, Koji Izunome, Kazuhiko Kashima
  • Patent number: 7175911
    Abstract: The invention provides titanium dioxide fine particles, wherein nitrogen and at least one element selected from carbon, hydrogen, sulfur doped in titanium dioxide by heat-treating fine particles of a material of titanium dioxide at 500° C. or more and 600° C. or less in a reducing gas atmosphere containing nitrogen. The titanium fine particles exhibit a high photocatalytic activity than in the conventional art by irradiating a visible light such that they exhibit an isopropanol oxidation activity induced by visible light irradiation with a wavelength of 400 nm or more and 600 nm or less with excellent stability and durability of the photocatalytic activity.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: February 13, 2007
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Zhonghua Zhou, Fumio Tokuoka, Yugo Ito, Tatsuya Ishii, Shunzo Shimai, Hiroshi Yamaguchi, Hiroyuki Kondo
  • Patent number: 7149341
    Abstract: A wafer inspection apparatus has a supporting means (10) for rotatably supporting a wafer (W) formed of a disk, a circumferential edge imaging means (40) for imaging a circumferential edge (S) of the wafer (W) that is supported by the supporting means for rotation, a notch imaging means (50) for imaging a notch (N), a notch illumination part (52) for illuminating the notch (N), and a control means (70) for processing image data imaged by the circumferential edge imaging means (40) and the notch imaging means (50). The circumferential edge imaging means (40) has a plurality of imaging cameras (41) for imaging a plurality of different parts in a thickness direction of the circumferential edge of the wafer (W). The different parts of the circumferential edge (S) of the wafer (W) include an apex at right angles to a surface of the wafer (W) and a front side bevel and a back side bevel inclined relative to the apex.
    Type: Grant
    Filed: February 11, 2003
    Date of Patent: December 12, 2006
    Assignees: Toshiba Ceramics Co., Ltd., Shibaura Mechatronics Corporation
    Inventors: Yoshinori Hayashi, Hiroyuki Naraidate, Hiroaki Yuda, Atsushi Tanabe, Hiromichi Isogai, Koji Izunome
  • Patent number: 7090932
    Abstract: A plasma resistant member has a base material and a coating layer made of an Y2O3, the coating layer being formed on a surface of the base material. The coating layer has a thickness of 10 ?m or more and the Y2O3 of the coating layer contains solid solution Si ranging from 100 ppm to 1000 ppm.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: August 15, 2006
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Yoshio Kobayashi, Masahiko Ichishima, Yuu Yokoyama
  • Patent number: 7083677
    Abstract: Using a seed crystal comprising a silicon single crystal not including a vacancy excess region, a neck comprising a silicon single crystal not including a vacancy excess region is grown with a diameter contracted smaller than, or equal to that of the contact surface of the silicon seed crystal in contact with a raw material silicon melt, and necking is performed so that the length L of the neck satisfies L?d·(cot ?), where d denotes the length of the diameter or the diagonal of the contact surface of the silicon seed crystal in contact with the raw material silicon melt, and ? denotes the angle formed between the propagation direction of dislocations and the growth direction of the neck, and then the silicon single crystal is grown with the diameter expanded.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: August 1, 2006
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventor: Masayuki Watanabe
  • Patent number: 7082789
    Abstract: A silica glass member for semiconductor in which each concentration of Fe, Cu, Cr and Ni is 5 ppb or less and the concentration of an OH group is 30 ppm or less and which has a viscosity of 1013.0 poise or more at 1200° C. is provided as a silica glass member for semiconductor having high heat-resistance and higher purity.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: August 1, 2006
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Masanobu Ezaki, Lian-Sheng Pan, Seiji Taniike
  • Patent number: 7077905
    Abstract: An apparatus for pulling the single crystal has a radiation shield. The apparatus can improve the ratio of single crystallization, even if the radiation shield is made of graphite base material and covered with silicon carbide. The apparatus can be manufactured by low cost and can improve heat insulating characteristic. The apparatus does not generate cracks by heat stress even in a large size. In the apparatus for Czochralski method having the radiation shield, the radiation shield is formed of graphite base material covered with silicon carbide. An inside corner of a curvature formed on the base material is formed of a curved surface.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: July 18, 2006
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Makoto Shimosaka, Sunao Abe
  • Patent number: 7072578
    Abstract: A carbon wire heating element sealing heater is provided. Therein, a carbon wire heating element using carbon fibers is sealed in a quartz glass member, wherein absorption water quantity of the carbon wire heating element is 2×10?3 g/cm3 or less.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: July 4, 2006
    Assignees: Toshiba Ceramics Co., Ltd., Tokyo Electron Limited
    Inventors: Norihiko Saito, Hiroyuki Honma, Hiroshi Mori, Eiichi Toya, Tomio Konn, Tomohiro Nagata, Sunao Seko, Akira Otsu, Takanori Saito, Ken Nakao, Kazutoshi Miura, Harunari Hasegawa, George Hoshi, Katsutoshi Ishi
  • Patent number: 7060597
    Abstract: A manufacturing method for a silicon substrate having a strained layer, has steps of forming a plurality of atomic steps having a height of 0.1 nm or more on the surface of a silicon substrate, forming a plurality of terraces having a width of 0.1 ?m or more between the plurality of atomic steps and forming a SiGe layer or a SiGe layer and a Si layer on the silicon substrate.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: June 13, 2006
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Hisatsugu Kurita, Masato Igarashi, Takeshi Senda, Koji Izunome
  • Patent number: 7048796
    Abstract: At the time of fabricating a silicon single crystal wafer from a nitrogen-doped silicon single crystal grown according to the Czochralski method, a silicon single crystal wafer covered with a region in which an oxygen precipitation bulk micro defect and an oxidation induced stacking fault mixedly exist is subjected to heat treatment at a temperature of 1100 to 1300° C. in a reducing gas or inert gas atmosphere. In such a manner, a method of fabricating a high-quality silicon single crystal wafer and a silicon single crystal wafer in which no grown-in crystal defects exist in the whole surface and oxygen precipitation bulk micro defects (BMD) are formed at a sufficiently high density to display the IG effect on the inner side can be provided. The single crystal wafer can be suitably used to form an operation region of a semiconductor device.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: May 23, 2006
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Masayuki Watanabe, Junichi Osanai, Akihiko Kobayashi, Kazuhiko Kashima, Hiroyuki Fujimori
  • Patent number: 6976908
    Abstract: A polishing head includes a head body, a first recessed portion formed in the lower surface of the head body, a support plate which can be moved up and down in the first recessed portion, a first film-like member in which a first space is formed between the upper surface of the support plate and the head body, a second recessed portion formed in a lower surface of the support plate, a second film-like member, in which a second space is formed between the second film-like member and the support plate, and which holds a wafer on the lower, a communicating hole which is formed in the support plate to communicate the first space with the second space, and a gas supply device which increases pressures in the first and second spaces with a fluid to equal pressures to bring the object into press contact with the polishing pad.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: December 20, 2005
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Ceramics Co., LTD
    Inventors: Takayuki Masunaga, Shinobu Oofuchi, Hiromichi Isogai, Katsuyoshi Kojima
  • Publication number: 20050244324
    Abstract: By uniformly forming an indefinite number of microscopic acicular crystals on a surface of a silicon substrate so as to be perpendicular to the surface of the substrate by plasma CVD method using a catalyst, it is possible to reliably, homogeneously and massively form an ultramicroscopic acicular silicon crystal having a substantial cone shape tapered so as to have a radius of curvature of not less than 1 nm to no more than 20 nm at its tip end and having a diameter of bottom surface of not less than 10 nm, and a height equivalent to or more than the diameter of bottom surface, at a desired location.
    Type: Application
    Filed: September 4, 2003
    Publication date: November 3, 2005
    Applicants: Toshiba Ceramics Co., Ltd., Techno Network Shikoku Co., Ltd.
    Inventors: Akimitsu Hatta, Hiroaki Yoshimura, Keiichi Ishimoto, Hiroaki Kanakusa, Shinichi Kawagoe
  • Patent number: D604257
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: November 17, 2009
    Assignees: Tokyo Electron Limited, Toshiba Ceramics Co., Ltd.
    Inventors: Yasuhiro Inatomi, Kenichi Yamaga, Hiroyuki Honma