Abstract: A method for compensating for gain changes of an N-level pulse amplitude modulation (PAM-N) modulated signal. The method comprises comparing the PAM-N modulated signal to N?1 configurable thresholds, wherein the input PAM-N modulated signal is also equalized and the N?1 configurable thresholds are N?1 different voltage levels; tracking gain changes in the input PAM-N modulated signal by comparing the input PAM-N modulated signal to a compensation threshold; and adjusting a level of the at least one of the N?1 configurable thresholds of the N?1 comparators based on an output of the compensation comparator, thereby offsetting a crossing point of the at least one comparator respective of the at least one of the N?1 configurable thresholds to compensate for gain changes in the input PAM-N modulated signal.

Abstract: A decision feedback equalizer (DFE) for equalizing PAM-N signals comprises a coefficient setting unit for setting a first group of most significant feedback coefficients of the DFE to a predefined value selected from a group of predefined values; a coefficients computation unit coupled to the coefficient setting unit for computing values of feedback coefficients of a second group of feedback coefficients other than the first group of most significant feedback coefficients; a feedback (FB) unit for mitigating, using a complete group of feedback coefficients, effects of interference from data symbols that are adjacent in time to an input data symbol, wherein most significant feedback coefficients of the first group are set to an optimal value computed during an initialization of the DFE and feedback coefficients of the second group are computed by the coefficients computation unit.

Abstract: An interface circuit for enabling clock and data recovery (CDR) of N-level pulse amplitude modulation (N-PAM) modulated data streams using a 2-PAM CDR circuit. The circuit comprises a number of N?1 comparators for comparing an input data stream to N?1 configurable thresholds, the input data stream is N-PAM modulated and the N?1 configurable thresholds are N?1 different voltage levels; a number of N?1 of edge detectors respectively connected to the N?1 comparators for detecting transitions from one logic value to another logic value, N is a discrete number greater than two; and a determination unit for determining if the detected transitions is any one of a major transition and a minor transition and asserting a transition signal if only a major transition or a minor transition has occurred, the transition signal is fed into a 2-PAM CDR circuit and utilized for recovering a clock signal of the input data stream.

Abstract: A PAM-N decision feedback equalizer (DFE) comprises a coefficient computation unit; a feedback unit that mitigates, using computed feedback coefficients, effects of interference from data symbols; an error-and-decision unit for at least computing a least error value respective to one of a plurality of decision levels, wherein the least error value indicates a difference of a pseudo equalized input PAM-N data symbol from an optimal position of the one of the plurality of decision levels, wherein the one of the plurality of decision levels corresponds to a modulation level used to modulate data in the input PAM-N data symbol; and a calibration unit for adaptively setting the plurality of decision levels based, in part, on the least error value, thereby enabling for compensating for gain changes resulted by a cable on which the input PAM-N data symbol is received and further compensating for embedded offsets of the error-and-decision unit.

Abstract: A Fast Ethernet and HDMI Ethernet channel (HEC) physical layer circuit. The physical layer circuit comprises a Fast Ethernet physical layer module implementing a physical layer specification of a Fast Ethernet communication standard; a hybrid circuit connected to the fast Ethernet physical layer module using a first twisted-pair wire and a second twisted-pair wire and capable of processing transmit and receive HDMI Ethernet channel (HEC) signals concurrently transported over a third twisted-pair wire; a switch for bypassing the hybrid circuit; and a controller for controlling the operation the hybrid circuit and the switch according to the operating mode of the physical layer circuit, wherein the operation mode of the physical layer circuit is any of a fast Ethernet and a HEC.

Abstract: An adaptive equalizer for high-speed serial data comprises a programmable equalizer for equalizing an input serial data signal to generate an equalized serial data signal, wherein the equalization is based on an optimal equalization mode; a signal quality meter for computing an eye width indication based on the equalized serial data signal, wherein the eye width indication is an indicative of the quality of the equalized serial data signal; and a decision unit for determining the optimal equalization mode based on the eye width indication.

Abstract: An apparatus for swapping output high-speed multimedia signals. In one embodiment the apparatus comprises a plurality of inputs coupled to a multimedia transmitter; a plurality of outputs coupled to a plurality of pins of a multimedia interface connector; and a controller for generating a control signal for configuring an order in which the plurality of inputs are routed to the plurality of outputs, wherein the order in which the plurality of inputs are routed to the plurality of outputs is set to enable un-crossing of one or more conducting wires coupling the plurality of inputs to the multimedia transmitter and to enable un-crossing of one or more conducting wires coupling the plurality of outputs and the plurality of pins of the multimedia interface connector.

Abstract: A system and method for transferring high-definition multimedia signals over four twisted-pairs. The system includes a multimedia source for transmitting multimedia data and source-to-sink management data to a multimedia sink over a first channel, a second channel and a third channel wherein the multimedia source is further being capable of transmitting a clock signal to the multimedia sink over a fourth channel; and a multimedia sink for transferring sink-to-source management data to the multimedia source over the fourth channel. The clock signal and the sink-to-source management data are simultaneously transmitted over the fourth channel. Each of the channels comprises a single twisted-pair, thereby the channels can bounded in a twisted pair type cable comprising at least one of: Category 5, Category 5e, Category 6, and Category 6e.

Abstract: An interface circuit for enabling clock and data recovery (CDR) of N-level pulse amplitude modulation (N-PAM) modulated data streams using a 2-PAM CDR circuit. The circuit comprises a number of N?1 comparators for comparing an input data stream to N?1 configurable thresholds, the input data stream is N-PAM modulated and the N?1 configurable thresholds are N?1 different voltage levels; a number of N?1 of edge detectors respectively connected to the N?1 comparators for detecting transitions from one logic value to another logic value, N is a discrete number greater than two; and a determination unit for determining if the detected transitions is any one of a major transition and a minor transition and asserting a transition signal if only a major transition or a minor transition has occurred, the transition signal is fed into a 2-PAM CDR circuit and utilized for recovering a clock signal of the input data stream.

Abstract: A multimedia interface cable for achieving complete interoperability between different types of multimedia display interfaces. The cable comprises a first multimedia connector including a plurality of contact pins of at least high-speed multimedia signals and control signals; a second multimedia connector including a plurality of contact pins of least high-speed multimedia signals and control signals; a plurality of un-crossing conducting wires for coupling the plurality of contact pins of the high-speed multimedia signals in the first multimedia connector to the plurality of contact pins of the high-speed multimedia signals in the second multimedia connector; and a plurality of conducting wires for coupling the plurality of contact pins of the control signals in the first multimedia connector to the plurality of contact pins of the control signals in the second multimedia connector.

Abstract: A method for designing a video processor with a variable and programmable bitwidth parameter. The method comprises selecting logical operations having propagation delay that scales linearly with the bitwidth; determining a desired tradeoff curve; and grouping instances of a logic operation having same properties; for a single instance of each logic operation, matching an actual curve of the logic operation to the desired tradeoff curve, wherein the actual curve is determined by the propagation delay and bitwidth of the logic operation.

Abstract: According to the methods of the invention, a further delayed DLL signal is compared to the reference clock and a delayed reference clock signal is compared to a DLL signal. These two comparisons are performed on the 360° signal and on the 180° signal. The delay introduced by the methods of the invention is preferably adjustable based on the results of a process monitor test. The process monitor test can be run continuously and accounts for process, voltage and temperature. The methods of the invention can also be used to test for clock skew in a clock tree on a chip.

Abstract: A uniform method for implementing multiple tunneling protocols in a switch or router is disclosed. The method is based on the realization that although the tunneling protocols are very different, they do share a similar overall structure which can be exploited to create a unified method of dealing with multiple protocols. By using similar data structures to implement multiple protocols, the invention makes data management and programming simple and, therefore, cost effective. According to the invention, all tunneling protocols are abstracted as the mapping of input L2 or L3 streams with output L2 or L3 streams. Mapping is provided by a finite set of tunnel interfaces. The tunnel interfaces map the input streams to output interfaces. As traffic streams flow through these interfaces, they are processed according to defined attributes of these interfaces.

Abstract: Write logic and read logic are coupled to SDRAM and a frame status table. VCG members are written into SDRAM by the write logic and an entry (based on the MFI and SQ) in the frame status table is maintained by the write logic for each member. The read logic scans the frame status table to identify the earliest frame number for which data is available in SDRAM. Based on the frame status and the address pointer offset, the read logic maintains a state table entry for each VCG member and a state for each VCG. According to the preferred embodiment, the read logic is provided in two parts separated by a temporary buffer. The first part of the read logic performs the functions described above and writes chunk data into the temporary buffer. The second part of the read logic reads byte data from the temporary buffer according to a selectable leak rate.

Abstract: A method buffering packets in a packet switching network (FIG. 5) includes receiving a packet from the network; splitting the packet into a plurality of PDUs; stripping at least some of the PDUs over a plurality of memory banks; (18) retrieving the PDUs from the memory banks: and at least temporarily storing the retrieved PDUs in the sequence they are to be transmitted. An apparatus for implementing the method is also disclosed.

Abstract: Methods for providing flow control of signal streams over a single full duplex ETHERNET link include receiving multiple data streams over a single ETHERNET link, associating a buffer with each data stream, putting received data into the appropriate buffer, monitoring the fullness of the buffers, and transmitting a PAUSE frame to the source of the data streams where the PAUSE frame indicates the fullness of each buffer. The PAUSE frame is read and where indicated, the transmission of data destined for a congested buffer(s) is halted until a subsequent PAUSE frame is received which indicates that the congested buffer(s) has become decongested. Apparatus for performing the methods are also provided.

Abstract: An apparatus for implementing VCAT in both SDH and PDH signals includes an SDH VCAT mapper coupled to a first telecom bus and a plurality of PDH units coupled to the first telecom bus and a second telecom bus. The PDH units read SDH VCAT bytes from the first telecom bus and write PDH VCAT bytes to the second telecom bus according to a gapped clock. At the data sink RS-Ack is determined before deskewing and is latched to be reported after deskewing. During deskewing, less than the maximum delay between members is tracked, thereby using less storage. Addressing of the deskewing storage is computed using a remainder algorithm.

Abstract: Time multiplexed processing of multiple SONET signals uses the same shared circuitry for framing, descrambling, maintenance signal processing, control byte processing and extraction, pointer tracking, retiming, and alarm indication. The signals are deserialized and multiplexed onto a byte-wide bus from which they are processed in a shared pipeline. Additional pipelines allow scaling up to higher capacity SONET signals. Each pipeline is provided with means for communicating with the other pipelines so that information derived from the processing of one stream can be shared with the processing of other streams when necessary. According to the presently preferred embodiment, bytes pass through the pipeline in five clock cycles.

Abstract: An apparatus for fast failure switch over in an ETHERNET switch includes redundant switch (trunk) ports (a main and a backup) and hardware and software logic for redirecting traffic to the backup port when the main port (or the link associated with it) fails. The switchover is immediate and is based on the content of a local status register which indicates the port (link) status. Thus, frames addressed to the dead port are redirected to the backup port and few frames are lost. The STP function may proceed concurrently and eventually no more frames are addressed to the dead port.

Abstract: Combined hardware and software processing is applied in an end node of the network which includes mapping/demapping and deskewing. Most of the LCAS procedure is implemented in software so that it can be modified easily. Some of the procedure is implemented in hardware to meet stringent timing requirements. In particular, the handshaking protocol is implemented in software and the procedure for actually changing of the link capacity in response to the handshaking is implemented in hardware. The hardware and software communicate via a shared memory which includes a receive packet FIFO, receive control and status registers, a transmit packet FIFO, transmit control and status registers, and a transmit time slot interchange table.