Abstract: A method and apparatus for reliably detecting both AIS and AIS-CI signals in the presence of a bit error ratio up to 1×10−3 includes an AIS detector having an AIS indication output, a CI detector having a CI indication output, and a two signal AND gate having its inputs coupled to the respective outputs of the detectors and having an output indicative of an AIS-CI detection. The AIS detector has an adjustable zero threshold and the CI detector has a threshold output coupled to the AIS detector for adjusting the zero threshold. According to the method of the invention, the AIS detector zero threshold is normally set at the normal threshold (1×10−3) but is reset to a higher threshold (e.g., 2×10−3) when the CI detector detects the presence of the CI code word.

Abstract: A method for the fair and efficient transfer of variable length packets using fixed length “segments” utilizes a modified UTOPIA interface with three additional signals added, i.e. start of packet (SOP), end of packet (EOP), and most significant byte (MSB). Packets are broken into “segments” of fixed, but programmable, length. The start of a segment is marked by a pulse on the UTOPIA start of cell (SOC) signal line. The start of a packet is marked by a pulse on the SOP signal line. The end of a packet is marked by a pulse on the EOP signal line. According to a presently preferred embodiment, bytes are transferred via a 16-bit bus. When a packet ends with a single byte on the bus, the MSB signal line is asserted to distinguish it from a packet which ends with two bytes on the bus. The invention can be expanded to accommodate buses wider than 16-bits by making the EOP a multiple bit signal.

Abstract: A phase/frequency detector includes two D-Q flip-flops, an OR gate, and an exclusive NOR (XNOR) gate. The phase/frequency detector is used in conjunction with a clock dejitter PLL where the underflow and overflow flags from a FIFO are coupled to the inputs of the OR gate and the Q outputs of the flip-flops are coupled to the inputs of the XNOR gate. The Qb output of each flip-flop is coupled to the D input of the respective flip-flop. The recovered clock signal is coupled to the clock input of the first flip-flop and the output of the VCXO is coupled to the clock input of the second flip-flop. The SET input of the first flip-flop is coupled to the overflow flag and the RESET input of the first flip-flop is coupled to the underflow flag. The SET input of the second flip-flop is coupled to the output of the OR gate and the output of the XNOR gate is passed through the filter to the input of the VCXO.

Abstract: A debugging interface includes a pair of decoders and an event history buffer coupled to the sequencer of a processor. The first decoder is coupled to the program counter of the sequencer and the Instruction RAM of the processor. The second decoder is coupled to the cause register of the sequencer and the event history buffer is also coupled to the cause register. The first decoder provides a three bit real time output which is indicative of the processor activity on a cycle by cycle basis. The three bit output indicates seven different conditions: whether the last instruction executed by the processor was an inc, an exception, an exception with no event history buffer entry, or a branch taken, whether there has been no instruction executed since the last clock cycle, and whether a jump was an immediate jump or a jump to a register.

Abstract: A debugging interface includes a pair of decoders and an event history buffer coupled to the sequencer of a processor. The first decoder is coupled to the program counter of the sequencer and the Instruction RAM of the processor. The second decoder is coupled to the cause register of the sequencer and the event history buffer is also coupled to the cause register. The first decoder provides a three bit real time output which is indicative of the processor activity on a cycle by cycle basis. The three bit output indicates seven different conditions: whether the last instruction executed by the processor was an inc, an exception, an exception with no event history buffer entry, or a branch taken, whether there has been no instruction executed since the last clock cycle, and whether a jump was an immediate jump or a jump to a register.

Abstract: An asynchronous data transfer and source traffic control system includes a bus master and a plurality of bus users coupled to a bidirectional data bus. The bus master provides two clock signals to each bus user, a system clock and a frame clock. The frame clock designates the start of a frame. A frame format preferably includes fifteen or sixteen system clock cycles, the first of which is designated the request field and the last of which includes a grant field. One or more other cycles may be assigned control and/or routing information and the remainder of the cycles comprise a data field of fixed length. During the request field, any number of bus users may request access which is received by the bus master. During the grant field, the bus master grants access to a selected bus user for the entire data portion of the next frame. Which user is granted access to the next frame is determined according to an arbitration algorithm in the bus master which may be unknown to the bus users.

Abstract: Methods and apparatus for generating and clearing an excessive bit error rate (EBER) alarm are provided and utilize a reset window algorithm. The BIP-8 bytes (e.g., B2 bytes) of incoming data blocks (each block being B frames long) of an STSn telecommunications signal are monitored in an "idle state" for code violation counts (CV). Upon receiving a data block having a code violation count meeting or exceeding a code violation count threshold (CVSET), a counter is initialized in a "crossing calculation state", and a window comprising a plurality (W) of blocks is monitored. The counter counts the number of incoming blocks in the window having a CV which meets or exceeds CVSET. If in the crossing calculation state, the count meets or exceeds its own threshold (X), an alarm state is entered and an EBER alarm is set. If not, the system returns to the "idle state". Once in the alarm state, every received block is monitored for its code violation count.

Abstract: An SRTS clock recovery apparatus and method are provided. The apparatus broadly includes a controllable destination node clock generator such as a digitally controllable oscillator, a block for generating a local RTS-related value from the destination node clock and the system reference clock, and a comparator which compares the incoming RTS-related value to the local RTS related value to provide a feedback error or control signal which is used to adjust the controllable clock generator. If desired, a filter which filters the error signal can be provided in the loop. With the feedback loop as provided, when the destination node clock is faster than the source clock, the error signal will cause the destination node clock to slow, and vice versa.

Abstract: Circuit board insertion circuitry is used in conjunction with a staggered electrical connector. The insertion circuitry includes an isolated circuit which receives a high system voltage upon first stage contact between the card and a high voltage bus, and uses that high system voltage to tristate the output of a transceiver on the circuit board prior to second stage contact being made between the transceiver and the backplane data bus. Override circuitry for overriding the tristating effects of the isolating circuit are provided such that when the bias circuit which controls the transceiver output is properly powered, the bias circuit will control the transceiver output, and not the isolated circuit. Additional circuitry which isolates the circuit board so that a power fault on the board will not impact other boards on the backplane is also provided.

Abstract: A data independent AGC control circuit for telecommunication applications is provided and includes an AGC amplifier, a fixed gain amplifier, a capacitor, and first, second, and third control circuits. The AGC amplifier has a data input, a control input, and a data output. The capacitor is coupled to the control input, and the charge on the capacitor effectively controls the gain of the AGC amplifier. The first control circuit is coupled to the data output of the fixed gain amplifier and to the capacitor and increases the stored charge on the capacitor when the data output exceeds a desired peak voltage level. The second control circuit is similarly coupled between the data output of the fixed gain amplifier and the capacitor, and decreases the stored charge on the capacitor when the data output exceeds a threshold voltage (typically 1/2 the desired peak voltage level).

Abstract: A two stage desynchronizer is provided to receive a gapped data component of an STS-3C (STM-1) signal and provide therefrom an ungapped DS-4NA (E4) data signal. The first stage includes a data byte formation block which takes the gapped STS-3C payload data and formulates the data into bytes, a first FIFO which receives the bytes, and a first FIFO read controller which utilizes the STS-3C clock signal and causes bytes of data to be read out according to a schedule which reads bytes eight or nine times out of every ten STS-3C clock cycles. For each row (270 byte times) of the STS-3C frame, either 241 or 242 bytes are read out of the FIFO according to a slightly gapped schedule where the reading of the 242nd byte at least partially depends upon the number of stuffs in the signal and the pointer movements received. The second stage of the desynchronizer includes a second FIFO, a FIFO fullness measurement block, and a VCXO.

Abstract: In a system where a first telecommunications signal is mapped into a second telecommunications signal, where a FIFO is used to store first signal data bits which are being mapped into the second signal, and the number of bits stored in the FIFO (i.e., FIFO "depth") is used in determining whether to generate a stuff or destuff signal, jitter is partially limited by, upon receiving an indication that the payload pointer of the second signal is moving in a first direction, generating a compensative payload pointer movement of the first signal in a second direction which is opposite the first direction. Additional jitter is removed by suspending the FIFO measurement from the time of the pointer movement in the second telecommunications signal until after the pointer movement and byte stuff or byte destuff in the first telecommunications signal has been accomplished, at which time the FIFO measurement resumes.

Abstract: In a system where jitter in a first telecommunications signal (e.g., TUG-3) which is being mapped into a second telecommunications signal (e.g., STS-3C) is reduced by moving the TUG-3 pointer in the opposite direction of the pointer movement of the STS-3C signal, and by suspending FIFO measurement from the time of the STS-3C pointer movement until the next TUG-3 stuff or destuff, the improvement is in further limiting jitter by moving the measurement points for the TUG-3 FIFO measurements without conducting TUG-3 pointer movements when the TUG-3 pointer movement would otherwise be moved into or over the transport overhead of the TUG-3 signal. The TUG-3 pointer movement is held in abeyance until two additional pointer movements in the same direction are received, and then the jump is made. During that time however, the measurement points for the TUG-3 FIFO depth measurements are moved by a byte each time the TUG-3 pointer movement is received.

Abstract: Jitter is limited in the mapping of a first telecommunications signal into a second telecommunications signal, by, upon receiving an indication that the payload pointer of the second telecommunications signal is moving in a first direction, generating a compensative payload pointer movement of the first telecommunications signal in a second direction which is opposite the first direction. The invention has particular application to the mapping of three E3 telecommunications signals which are in the format of a TUG-3 signal into an STS-3C SONET telecommunications signal in the STM-1 VC-4 format. When the STS-3C signal requires a pointer movement due to frequency compensation in the system, a compensative pointer movement at the TUG-3 level avoids eight units of jitter in the TUG-3 signal which could adversely affect system performance.

Abstract: A programmable signal generating apparatus and method are provided such as for creating a continuous SONET signal. The apparatus preferably comprises a DRAM, a memory address register, a loop counter, an address stack, an instruction decoder, and a SONET data output interface. The DRAM stores a plurality of words at a respective plurality of memory locations. Each word is preferably comprised of three bytes of SONET data and a command byte. One or more command bytes specify a command, and a plurality of commands are decoded by the decoder to generate a plurality of program sequences. The program sequences cause the SONET data bytes which are part of the data words to be generated into continuous SONET frames. The SONET data bytes do not act as typical data operands in that they have no effect upon program operation, but are simply used to generate a SONET data stream.

Abstract: Pulse width controlled adaptive equalizers are provided for telecommunication signals which are routed over coaxial cables. The adaptive equalizers operate on the premise that a coaxial cable degrades a telecommunications signal by widening the pulse of the signal and decreasing the amplitude. The longer the cable is, the wider the pulse gets. Thus, by detecting the width of the pulse against a desired width, and feeding back the difference to a variable filter which can correct the pulse width, a pulse width controlled adaptive equalizer can be provided.

Abstract: A digital clock dejitter circuit has a RAM for receiving an incoming gapped signal, a digital, fractional RAM fullness gauge for tracking the average input and output rates to and from the RAM and for generating therefrom a control indication, and a controllable digital frequency generator for receiving a fast clock signal and the control indication, and for providing therefrom a substantially jitter-free clock signal at the same nominal rate as the incoming gapped signal. The RAM fullness gauge has write and read counters which track the movement of data into and out of the RAM, and a subtractor for taking the difference of the counters to obtain the integer value of the RAM depth. The controllable digital frequency generator has an adder, a register, and a fast clock counter (FCC) which provides the fullness gauge with a fractional digital indication of the RAM depth.

Abstract: Clock dejitter circuits are provided and comprise control circuits for generating a plurality of pulses over a clock cycle, and clock circuits for tracking the speeds of jittered incoming data signal and based on those speeds, and utilizing the plurality of pulses generating substantially unjittered data signals at the nominal rates of the jittered incoming signals. A control circuit broadly includes a divide by value x-divide by value x+1 circuit which receives a fast input clock signal, a modulus y counter, and a count decode for providing z control pulses over the count of y, and a logic gate for taking the outputs from the count decode and controlling the divide block to guarantee hat the divide block divides the fast input clock signal by value x q times for every r times the divide block divides the fast input clock signal by value x+1; wherein q plus r equals y, and z equals either q+1 or r+1.

Abstract: Methods and apparatus for quickly generating and transmitting SONET AIS signals are disclosed. Upon detecting a failure condition at the receiving side of a SONET terminating equipment, the SONET terminating equipment inserts an internal alarm control signal (e.g. a byte of all ones) into at least one predetermined transport overhead timeslot (e.g. E1). On the transmitting side, the transmitting SONET terminating equipment monitors the predetermined timeslot(s) and detects whether an indication of the internal alarm control signal has been received. If so, the transmitting SONET terminating equipment inserts an appropriate alarm in predetermined overhead and data timeslots of the outgoing SONET frame signal as specified by proposed AIS standards.

Abstract: Apparatus and methods for concatenating a plurality of lower level SONET signals into higher level SONET signals are provided. In generating a higher level SONET signal (e.g., STS-12C) using a plurality of lower level SONET signal processing apparatus (e.g., STS-3 type terminators), the J1 bytes of each lower level signal are tracked through the FIFOs of the apparatus to provide J1 byte control signals, and a logic circuit is provided having phase 3 of the outgoing STS-3 clock, and the J1 byte control signals from all the STS channels of the higher level signal as inputs. The J1 byte control signals from all the channels are combined as a J1ANDcomposite by utilizing a single bus which is coupled to each of the apparatus. The logic circuit inhibits a read of a J1 byte from any particular FIFO unless the J1ANDcomposite signal is high at phase 3 of the clock.