Abstract: The present invention provides an array of parallel programmable processing engines interconnected by a switching network. At least some of the processing engines execute a thread, and at least some threads communicate with each other through communication objects either internally within one processing engine or through the network. A scheduling step of the parallel programmable processing engines is initiated by one or more events, an event being defined by a change of a state variable of a communication object. The array comprises: means for scheduling a scheduling step of the processing engines, the scheduling means comprising means for executing at least a first set of threads in parallel, means for updating state values of communications objects in response to the parallel executing step, and means for repeatedly and sequentially scheduling the executing means and the updating means until no more events occur. The present invention also provides a deterministic method of operating such an array.

Abstract: According to the methods of the invention, a further delayed DLL signal is compared to the reference clock and a delayed reference clock signal is compared to a DLL signal. These two comparisons are performed on the 360° signal and on the 180° signal. The delay introduced by the methods of the invention is preferably adjustable based on the results of a process monitor test. The process monitor test can be run continuously and accounts for process, voltage and temperature. The methods of the invention can also be used to test for clock skew in a clock tree on a chip.

Abstract: A packet scheduling method and apparatus is described for enqueuing incoming data packets in sessions, and for storing the sessions in sequential order in service-groups. Each service-group is assigned a nominal service-interval in which time a data packet is to be transmitted, the nominal service-interval of one service-group being faster than the nominal service-interval of another service-group. Within one service-group, one session is serviced until the nominal service-interval of any of the service-groups where there is at least one data packet to be sent is exceeded.

Abstract: Methods for retiming SONET signals include demultiplexing STS-1 signals from an STS-N signal, buffering each of the STS-1 signals in a FIFO, determining the FIFO depth over time, and determining a pointer leak rate based in part on FIFO depth and also based on the rate of received pointer movements. According to the presently preferred embodiment, each FIFO is 29 bytes deep. If FIFO depth is 12-17 bytes, no leaking is performed. If the depth is 8-12 bytes or 17-21 bytes, a slow leak rate is set. If the depth is 4-8 bytes or 21-25 bytes, a fast leak rate is set. If the depth is 0-4 bytes or 25-29 bytes, pointer movements are immediate. The calculated leak rates are based on the net number of pointer movements (magnitude of positive and negative movements summed) received during a sliding window of n×32 seconds (n×256,000 frames).

Abstract: Methods for implementing a backpressure mechanism in an asynchronous data transfer and source traffic control system include detecting when a bus user is experiencing congestion and preventing other bus users from sending cells over the bus. According to a first embodiment, if congestion is detected for two consecutive frames, the arbiter is inhibited from granting access to any bus user for one frame. According to a second embodiment, if congestion is detected during any frame, all the bus users are prevented from transmitting low priority traffic until congestion is absent for four consecutive frames. An apparatus for performing the methods is also disclosed.

Abstract: Apparatus for simultaneously transferring synchronous and asynchronous signals among broadband access devices includes a data bus, a clock bus, and a plurality of control lines which are used to indicate the type of data being carried on the bus. According to the methods of the invention, data is transferred on the bus in a repeating frame having a plurality of slots, each slot being defined as one bus clock cycle. Each slot may contain a synchronous or asynchronous data signal and one or more of the control lines are asserted during the slot time of the data to indicate the type of data. Two embodiments are provided. One utilizes a 25 MHz clock bus and a repeating frame of three hundred thirty-six slots. The other utilizes a 75 MHz clock bus and a repeating frame of one thousand eight slots.

Abstract: Methods and apparatus for providing redundancy in an asynchronous data transfer and source traffic control system include configuring a primary client and a backup client with the same receive address but different transmit addresses. This allows both clients to receive the same traffic flows by utilizing a common receive address while maintaining independent transmit identity allowing each client to communicate with other clients in the system. The methods of the present invention are compatible with a CellBus® system operating in either 16-client mode or 32-client mode.

Abstract: Methods for correcting errors in a GFP-T superblock include buffering the 64 bytes of data in an 8×8 byte buffer, buffering the flag byte in a separate buffer, calculating the CRC remainder, and performing single and double bit error correction in three stages. In the first stage, the CRC remainder is compared to a single bit error syndrome table and if an error is located, it is corrected. In the second stage, the CRC remainder is compared to a double bit error syndrome table and if an error is located, it is corrected. The third stage corrects the second error of a double bit error. The flag byte is processed first, followed by the data bytes, eight bytes at a time.

Abstract: A SONET demapper includes three desynchronizers, each of which includes a RAM-based, shared digital phase locked loop, shared elastic storage, and twenty-eight divide-by 33/34/44/45 counters. Unlike a conventional desynchronizer which uses separate FIFOs for each of the twenty-eight T1/E1 channels, the elastic storage for each channel is an addressed portion of a shared block of RAM. Each desynchronizer generates a clock for each of the twenty-eight T1/E1 channels based on a FIFO depth count for each channel which is derived from a read pointer, an “effective write pointer”, and the divide-by clock for the channel. Each desynchronizer can desynchronize both T1/E1 signals as well as a combination of these signals. In addition, the invention combines the leak FIFO and desynchronizer FIFO into a single FIFO with an effective write pointer. This eliminates the need to maintain separate counters and pointers for separate FIFOs.

Abstract: A cross-connect switch (1000) is adapted for a plurality of input channels in a synchronous network. Each input channel has a pointer processor (800) including a pointer interpreter (802), an elastic store buffer (804), and a pointer generator (806). The cross-connect switch (1000) further comprises a memory-less space switch (1020) interposed between a plurality of pointer interpreters (1010) and a plurality of elastic store buffers (1030). The space switch (1020) switches selected outputs of the plurality of pointer interpreters (1010) to inputs of each elastic store buffer (1000) in response to a switching control signal.

Abstract: Methods and apparatus for supporting multiple UTOPIA bus masters on a single UTOPIA bus include coupling two UTOPIA bus masters via three signal lines (Ready, Request, and Grant), designating one of the masters a primary master and the other a secondary master, and coupling both bus masters to the same UTOPIA bus. When receiving cells from the UTOPIA bus, both masters accept cells and screen them (with a lookup table) to determine which cells are addressed to them. When transmitting cells, the primary master normally controls polling and PHY selection. The secondary master asserts the Request line during polling to indicate that it has a cell to send to a PHY that has responded positively to the polling. In response to the Request signal, the primary master asserts the Grant line and control of the bus is given to the secondary master for the next cell cycle. The presently preferred embodiment utilizes an arbitration scheme to assure fairness in allocating control of the bus.

Abstract: A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12×12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned.

Abstract: Methods for extracting packetized data from a SONET/SDH signal include processing the signal to produce a deskewed data stream; demapping the data stream to produce a stream of packets; and temporarily storing the packets in a packet buffer, wherein the demapping is performed at a first rate when the fullness of the buffer is below a fullness threshold and the demapping is performed at a second rate when the fullness of the buffer is at or above the fullness threshold. Apparatus for performing the methods are also disclosed.

Abstract: The methods of the invention include providing a state machine on chip with a SONET/SDH mapper and providing means whereby a plurality of members of a VCG can share the same state machine. The apparatus of the invention preferably includes a “smart” time wheel for granting access to the single state machine and memory for storing state information for each of the VCG members. A TCM (transmit configuration management) block is provided which interrelates the state change of one member with all of the other members of the VCG by reference to a plurality of status registers, one for each member of the VCG. The TCM block includes a single module which is shared by all VCG members. The “smart” time wheel is connected not only to the shared state machine but also to the single TCM module and the status and configuration registers.

Abstract: Methods for allocating bandwidth among MCR and best effort connections include listing MCR connections in an MCR service list and best efforts connection in a best efforts (BE) service list. Assigning an MCR value to each MCR connection and setting a Cell Count Register (CCR) with it. During a service interval, dequeueing each MCR connection queue in round robin fashion according to the MCR service list and decrementing the associated CCR. If the CCR reaches zero before the end of the service interval and there are still cells in the queue, the connection is moved from the MCR service list to the BE service list for the remainder of the service interval. If the CCR reaches zero before the end of the service interval and/or there are no cells remaining in the queue, the connection is removed from the MCR service list.

Abstract: Methods and apparatus for the hardware implementation of virtual concatenation and link capacity adjustment over SONET/SDH frames include providing a state machine on chip with a SONET/SDH mapper and providing means whereby a plurality of members of a VCG can share the same state machine. The apparatus of the invention preferably includes a time wheel for granting access to the single state machine and memory for storing state information for each of the VCG members. According to the presently preferred embodiment, the invention is implemented on chip with an OC-3 Ethernet mapper. Up to eighty-four VCG members share the same state machine and memory is provided on the chip for maintaining the state information for eighty-four VCG members. Fifteen bits are used to store the state information for each VCG member in low order and seventeen bits are used to store the state information for each VCG member in high order. The presently preferred time wheel runs at 20 MHz.

Abstract: Methods and apparatus for extending the transmission range of a UTOPIA ATM (or packet) interface include providing two UTOPIA extension devices, one for coupling a PHY layer device to a transmission cloud and one for coupling an ATM layer (or LINK layer) device to the transmission cloud. Each device includes a UTOPIA interface emulator, a link controller, and a media transceiver. The media transceiver can be made to support various media such as a backplane, copper cable, optical fiber, or a wireless medium. The UTOPIA extension device preferably includes a UTOPIA inlet buffer, a UTOPIA outlet buffer, an inlet clock decoupling buffer, an outlet clock decoupling buffer, and a flow control module. The UTOPIA inlet and outlet buffers are used for traffic management and the clock decoupling buffers allow the UTOPIA interface emulator and the link controller to operate in different clock domains. The link controller provides error control and backpressure delivery to support flow control.

Abstract: A packet scheduling method and apparatus is described for enqueuing incoming data packets in sessions, and for storing the sessions in sequential order in service-groups. Each service-group is assigned a nominal service-interval in which time a data packet is to be transmitted, the nominal service-interval of one service-group being faster than the nominal service-interval of another service-group. Within one service-group, one session is serviced until the nominal service-interval of any of the service-groups where there is at least one data packet to be sent is exceeded.

Abstract: An apparatus for guaranteeing MCR in an ATM device includes at least one queue for each service category, a scheduler for dequeuing cells from the queues, a queue status block for indicating which queues are empty, and an MCR service block. The MCR service block includes a plurality of timers, at least one for each service category. According to the methods of the invention, an MCR value is selected for each queue (or service category) and a timer in the MCR service block is set according to the MCR value. The scheduler dequeues cells in strict priority from non-empty queues as determined by the queue status block. The scheduler is preempted, however, by the MCR service block when a queue fails to be serviced before its associated timer expires. The arrangement of queues and associated timers is subject to alternate embodiments.

Abstract: An integrated circuit chip is provided with a JTAG TAP, an on-chip JTAG master coupled to the JTAG TAP and a microprocessor interface coupled to the JTAG master. This arrangement permits testing the integrated circuit chip without removing it from a circuit board or taking the circuit board out of service. It allows testing without regard to other chips on the same board. Preferably, the chip also has a conventional JTAG interface which is switchably uncouplable from the JTAG TAP.