Patents Assigned to United Microelectronics Corporation
  • Patent number: 10199232
    Abstract: Exemplary metal line structure and manufacturing method for a trench are provided. In particular, the metal line structure includes a substrate, a target layer, a trench and a conductor line. The target layer is formed on the substrate. The trench is formed in the target layer and has a micro-trench formed at the bottom thereof. A depth of the micro-trench is not more than 50 angstroms. The conductor line is inlaid into the trench.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Shin-Chi Chen, Jiunn-Hsiung Liao, Yu-Tsung Lai
  • Patent number: 10128366
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: November 13, 2018
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yu-Ying Lin, Kuan Hsuan Ku, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu Lin, Chun Yao Yang, Yu-Ren Wang, Neng-Hui Yang
  • Patent number: 10121869
    Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device formed from the manufacturing method includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: November 6, 2018
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Weichang Liu, Zhen Chen, Shen-De Wang, Wang Xiang, Wei Ta
  • Patent number: 10115582
    Abstract: Provided herein is a semiconductor device is provided. The semiconductor device includes a substrate including a MEMS region and a connection region thereon; a dielectric layer disposed on the substrate in the connection region; a poly-silicon layer disposed on the dielectric layer, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer; and a passivation layer covering the dielectric layer, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: October 30, 2018
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yan-Da Chen, Weng Yi Chen, Chang-Sheng Hsu, Kuan-Yu Wang, Yuan Sheng Lin
  • Patent number: 10103248
    Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into a first part and a second part; forming a STI structure in the trench; forming a first and a second polycrystalline silicon gate stack structures at the fin structure; forming discontinuous openings on the exposed fin structure and growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain and a source doped layers in the first and second parts respectively; and performing a RMG process to replace the first and second polycrystalline silicon gate stack structures with a first and second metal gate stack structures respectively.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: October 16, 2018
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Tai-Ju Chen, Yi-Han Ye, Te-Chih Chen
  • Patent number: 9978854
    Abstract: An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in a trench shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: May 22, 2018
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Jhen-Cyuan Li, Shui-Yen Lu, Man-Ling Lu, Yu-Cheng Tung, Chung-Fu Chang
  • Patent number: 9916978
    Abstract: The invention provides a method for fabricating a fin field effect transistor (FinFET), comprising: providing a substrate having a logic region and a large region; forming a plurality of fin structures in the logic region by removing a portion of the substrate in the logic region; forming an oxide layer on the substrate filling in-between the fin structures in the logic region; forming an first epitaxial structure in the large region by removing a portion of the substrate in the large region; exposing a portion of the fin structures and a portion of the epitaxial structure by removing a portion of the oxide layer; and forming a gate electrode on portions of the fin structures.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: March 13, 2018
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Wei-Chi Cheng, Ssu-I Fu, Jyh-Shyang Jenq, Chao-Hung Lin
  • Patent number: 9865693
    Abstract: A semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge. Additionally, a method of manufacturing the semiconductor memory device is also provided.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: January 9, 2018
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Weichang Liu, Zhen Chen, Shen-De Wang, Wang Xiang, Wei Ta
  • Patent number: 9852983
    Abstract: A fabricating method of an anti-fuse structure, comprising: providing a substrate having a first conductive plug and a second conductive plug separated from the first conductive plug; forming an amorphous silicon layer on the substrate, wherein a portion of the amorphous silicon layer overlapping the first conductive plug is defined as a first region, and a portion of the amorphous silicon layer overlapping the second conductive plug is defined as a second region; performing an implantation process to the first region and the second region, wherein the first region has a higher doping concentration than the second region; forming a titanium nitride layer on the amorphous silicon layer; and patterning the titanium nitride layer and the amorphous silicon layer.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: December 26, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventor: Dai Yang Lee
  • Patent number: 9793105
    Abstract: The invention provides a fabricating method of a FinFET, comprising: providing a substrate having fin structures; depositing an dielectric layer on the substrate filling between the fin structures; forming recesses to reveal a portion of the fin structure by removing a portion of the dielectric layer; performing a cleaning process on using a cleaning solution selected from one of a first solution, consisting of dHF and H2O2, and a second solution, consisting of dHF and DIO3; forming a gate structure across on the fin structures; and forming a source/drain structure on the substrate at two lateral sides of the gate structure. The present invention also provides a fabricating method of a FinFET having an improved cleaning step using a cleaning solution having one of a third solution, consisting of dHF and DIO3, and a fourth solution, consisting of NH4OH and DIO3 before formation of the source/drain structure.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: October 17, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chun-Wei Yu, Hsu Ting, Chueh-Yang Liu, Yu-Ren Wang, Kuang-Hsiu Chen, Yi-Liang Ye
  • Patent number: 9780193
    Abstract: A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: October 3, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chia-Lin Lu, Yu-Cheng Tung, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Publication number: 20170271153
    Abstract: The invention provides a method of epitaxial structure formation in a semiconductor, comprising: providing a substrate; performing a dry etch to form a first recess; after performing the dry etch, performing a SPM cleaning process on the substrate by using a nozzle spraying SPM solution with an angle greater than zero and less than 45 degrees relative to the substrate; after performing the SPM cleaning process, performing a wet etch to form a second recess; after performing the wet etch, performing a pre-epi cleaning process; and growing an epitaxial structure in the second recess.
    Type: Application
    Filed: March 15, 2016
    Publication date: September 21, 2017
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventor: TSUNG-HSUN TSAI
  • Patent number: 9768017
    Abstract: The invention provides a method of epitaxial structure formation in a semiconductor, comprising: providing a substrate; performing a dry etch to form a first recess; after performing the dry etch, performing a SPM cleaning process on the substrate by using a nozzle spraying SPM solution with an angle greater than zero and less than 45 degrees relative to the substrate; after performing the SPM cleaning process, performing a wet etch to form a second recess; after performing the wet etch, performing a pre-epi cleaning process; and growing an epitaxial structure in the second recess.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: September 19, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventor: Tsung-Hsun Tsai
  • Patent number: 9735015
    Abstract: A method of manufacturing a semiconductor structure, comprising: providing a preliminary structure having a first region and a second region and comprising a plurality of first trenches in the first region; forming a metal layer filling the first trenches covering on the preliminary structure, wherein the metal layer comprises a concave portion in the second region and the concave portion defines an opening; forming a metal nitride layer on the metal layer by an nitride treatment; and performing a planarization process to remove the metal nitride layer and a portion of the metal layer to expose the preliminary structure.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: August 15, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kun Ju Li, Hsin Jung Liu, Wei-Chuan Tsai, Min-Chuan Tsai, Yi Han Liao, Chun-Tsen Lu, Chun-Lin Chen, Jui-Ming Yang, Kuo-Chin Hung
  • Patent number: 9716165
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: July 25, 2017
    Assignee: United Microelectronics Corporation
    Inventors: Yu-Ying Lin, Kuan Hsuan Ku, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu Lin, Chun Yao Yang, Yu-Ren Wang, Neng-Hui Yang
  • Patent number: 9678530
    Abstract: An clock skew adjusting structure is provided. The clock skew adjusting structure includes a substrate, a wiring structure, a first active component and a second active component. The wiring structure includes at least a wiring layer and at least a via, the via is configured for different wiring layers to be electrically connected with each other. The first active component is formed on the substrate and configured for delivering a clock signal to the wiring structure. The second active component is formed on the substrate and electrically connected to the first active component through the wiring structure thus forming a timing path. The second active component receives the clock signal through the timing path.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: June 13, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventor: Chien-Hung Chen
  • Patent number: 9660086
    Abstract: The present invention provides a fin-shaped field effect transistor (FinFET), comprises: a substrate having a fin structure; a plurality trenches formed on the fin structure with an alloy grown in the trenches; a gate structure on the fin structure perpendicular to an extending direction of the fin structure in-between the plurality of trenches; and an amorphous layer on a surface of the fin structure exposed by the gate structure and disposed in-between the gate structure and the alloy. The invention also provides a manufacturing method of a fin-shaped field effect transistor (FinFET).
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: May 23, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chun-Yu Chen, Chung-Ting Huang, Ming-Hua Chang, Tien-Chen Chan, Yen-Hsing Chen, Hsin-Chang Wu
  • Patent number: 9640663
    Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The high-voltage FinFET device includes: at least one fin structure, a working gate, a shallow trench isolation structure, and a first dummy gate. The fin structure includes a first-type well region and a second-type well region adjacent to the first-type well region, and further includes a first part and a second part. A trench is disposed between the first part and the second part and disposed in the first-type well region. A drain doped layer is disposed on the first part which is disposed in the first-type well region, and a source doped layer is disposed on the second part which is disposed in the second-type well region. The working gate is disposed on the fin structure which is disposed in the first-type well region and in the second-type well region.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: May 2, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Tai-Ju Chen, Yi-Han Ye, Te-Chih Chen
  • Patent number: 9634125
    Abstract: A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: April 25, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yen-Liang Wu, Chung-Fu Chang, Yu-Hsiang Hung, Ssu-I Fu, Wen-Jiun Shen, Man-Ling Lu, Chia-Jong Liu, Yi-Wei Chen
  • Patent number: 9627210
    Abstract: A method of fabricating an electrostatic discharge protection structure includes the following steps. Firstly, a semiconductor substrate is provided. Plural isolation structures, a well region, a first conductive region and a second conductive region are formed in the semiconductor substrate. The well region contains first type conducting carriers. The first conductive region and the second conductive region contain second type conducting carriers. Then, a mask layer is formed on the surface of the semiconductor substrate, wherein a part of the first conductive region is exposed. Then, a first implantation process is performed to implant the second type conducting carriers into the well region by using the mask layer as an implantation mask, so that a portion of the first type conducting carriers of the well region is electrically neutralized and a first doped region is formed under the exposed part of the first conductive region.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: April 18, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chang-Tzu Wang, Yu-Chun Chen, Tien-Hao Tang