Patents Assigned to United Microelectronics Corporation
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Publication number: 20210036152Abstract: A new method for fabricating a semiconductor device with high selection phosphoric acid solution and eliminating the step of oxide removal and thus reducing oxide loss to improve yield gain and cost saving.Type: ApplicationFiled: August 2, 2019Publication date: February 4, 2021Applicant: United Microelectronics CorporationInventor: Tsung-Hsun Tsai
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Patent number: 9716165Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.Type: GrantFiled: June 21, 2016Date of Patent: July 25, 2017Assignee: United Microelectronics CorporationInventors: Yu-Ying Lin, Kuan Hsuan Ku, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu Lin, Chun Yao Yang, Yu-Ren Wang, Neng-Hui Yang
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Patent number: 9312357Abstract: A semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a first dielectric layer thereon. The first dielectric layer is provided with a trench. Then, a metal layer is formed to fill the trench and to cover the surface of the first dielectric layer. The metal layer is partially removed so that a remaining portion of the metal layer covers the first dielectric layer. A treatment process is performed to transform the remaining portion of the metal layer into a passivation layer on the top portion and a gate metal layer on the bottom portion. A chemical-mechanical polishing process is performed until the first dielectric layer is exposed so that a remaining portion of the passivation layer remains in the trench.Type: GrantFiled: October 16, 2014Date of Patent: April 12, 2016Assignee: United Microelectronics CorporationInventors: Shih-Chang Tsai, Tzu-Chin Tseng, Hsiao-Ting Lin, Chang-Yih Chen, Sam Lai
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Patent number: 9105355Abstract: A memory cell array includes a bit line, a complementary bit line, a first operation voltage supply circuit, a second operation voltage supply circuit, a first memory cell and a second memory cell. The first operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a first operation voltage. The second operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a second operation voltage. The first memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the first operation voltage. The second memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the second operation voltage. The first and second memory cells are located in a same column in the memory cell array.Type: GrantFiled: July 4, 2013Date of Patent: August 11, 2015Assignee: United Microelectronics CorporationInventor: Hsin-Wen Chen
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Patent number: 9107017Abstract: An etching method for manufacturing MEMS devices is provided. The method includes steps of: providing a substrate including a first surface and a second surface opposite to the first surface, wherein a base structure, a sacrificial structure and at least one adhesion layer are arranged on the first surface of the substrate, the adhesion layer is disposed between the base structure and the sacrificial structure, the base structure is disposed between the adhesion layer and the substrate; performing a surface grinding process on the second surface of the substrate; performing a first plasma etching process by using a first mixed gas to remove the sacrificial structure, wherein the first mixed gas includes oxygen and a first nitrogen-based gas; and performing a second plasma etching process by using a second mixed gas to remove the adhesion layer, wherein the second mixed gas includes a second nitrogen-based base gas and a fluorine-based gas.Type: GrantFiled: June 26, 2014Date of Patent: August 11, 2015Assignee: United Microelectronics CorporationInventors: Yu-Hsiang Chiu, Jeng-Ho Wang, Hsin-Yi Lu, Chang-Sheng Hsu
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Patent number: 9105582Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.Type: GrantFiled: August 15, 2013Date of Patent: August 11, 2015Assignee: United Microelectronics CorporationInventors: Hung-Lin Shih, Chih-Chien Liu, Jei-Ming Chen, Wen-Yi Teng, Chieh-Wen Lo
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Patent number: 9030221Abstract: A circuit structure of a test-key and a test method thereof are provided. The circuit structure comprises a plurality of transistors, a first conductive contact, a plurality of second conductive contacts and a plurality of third conductive contacts. The transistors are arranged in a matrix. The first conductive contact is electrically connected to one source/drain of each transistor in each column of the matrix. Each second conductive contact is electrically connected to the other source/drain of each transistor in a corresponding column of the matrix. Each third conductive contact is electrically connected to the gate of each transistor in a corresponding row of the matrix. In the method, a plurality of driving pulses are provided to the third conductive contacts in sequence, and a plurality of output signals are read from the second conductive contacts to perform an element-character analyzing operation when a row of the transistors is turned on.Type: GrantFiled: September 20, 2011Date of Patent: May 12, 2015Assignee: United Microelectronics CorporationInventor: Ching-Yu Tso
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Patent number: 9024407Abstract: A monitoring testkey for a wafer is provided. The monitoring testkey includes a first metal oxide semiconductor (MOS) transistor having a channel extending in a first direction, a second MOS transistor having a channel extending in a second direction, a common gate pad electrically connected to gate electrodes of the first MOS transistor and the second MOS transistor, a first source pad electrically connected to source electrodes of the first MOS transistor and the second MOS transistor, a first drain pad electrically connected to a drain electrode of the first MOS transistor, and a second drain pad electrically connected to a drain electrode of the second MOS transistor. The monitoring testkey helps to improve the critical dimension uniformity and electrical characteristics uniformity of elements in a wafer.Type: GrantFiled: December 7, 2011Date of Patent: May 5, 2015Assignee: United Microelectronics CorporationInventors: Chin-Chun Huang, Ji-Fu Kung, Wei-Po Chiu, Nick Chao
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Patent number: 9022392Abstract: An apparatus of semiconductor process including a chuck and a vacuum source is provided. The chuck has a plurality of holes for holding a semiconductor substrate, and the vacuum source is used for providing vacuum suction through the holes to make the semiconductor substrate be subjected to varied suction intensities according to a warpage level thereof.Type: GrantFiled: August 31, 2012Date of Patent: May 5, 2015Assignee: United Microelectronics CorporationInventors: Chung-Sung Jang, Ming-Tse Lin, Yung-Chang Lin
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Patent number: 9019672Abstract: A chip with electrostatic discharge protection function includes two power rails, a pin, a P-type FinFET, an N-type FinFET, two Fin-resistors, two diodes and an ESD unit. The pin is electrically connected to one power rail sequentially through one Fin-resistor and the P-type FinFET and electrically connected to the other power rail sequentially through the other Fin-resistor and the N-type FinFET. The two FinFETs are configured to have the control terminals thereof for receiving a transmission signal. The pin is further electrically connected to the two power rails through the two diodes, respectively. The ESD unit, electrically connected between the first and second power rails, is configured to provide an ESD path between the first and second power rails.Type: GrantFiled: July 17, 2013Date of Patent: April 28, 2015Assignee: United Microelectronics CorporationInventor: Shao-Ping Chen
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Patent number: 9004755Abstract: A temperature sensor includes a signal delaying apparatus, a comparison apparatus, a multiplier and a counting apparatus. The signal delaying apparatus is configured to receive a step signal, perform a phase delay operation on the received step signal according to a temperature degree, and thereby forming a first output signal. The comparison apparatus is configured to receive the first output signal and the step signal, and accordingly output a second output signal. The multiplier is configured to receive the second output signal and a clock signal, and accordingly output a third output signal. The counting apparatus is configured to receive the third output signal, count the number of pulses of the third output signal, and generate a digital code accordingly.Type: GrantFiled: July 23, 2012Date of Patent: April 14, 2015Assignee: United Microelectronics CorporationInventor: Shi-Wen Chen
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Patent number: 8970197Abstract: A voltage regulator circuit includes a plurality of transistors and a control circuit. Each transistor has two source/drain terminal and a gate terminal. One source/drain terminal of each transistor is electrically coupled to a source voltage, and the other source/drain terminals of the transistors are electrically coupled to each other and corporately referred to as an output terminal of the voltage regulator circuit. The control circuit is electrically coupled to the gate terminals of the transistors and configured to determine the number of the transistors to be turned on according to the difference between the voltage at the output terminal and a predetermined reference voltage.Type: GrantFiled: August 3, 2012Date of Patent: March 3, 2015Assignee: United Microelectronics CorporationInventor: Shi-Wen Chen
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Patent number: 8963202Abstract: A semiconductor ESD protection apparatus comprises a substrate; a first doped well disposed in the substrate and having a first conductivity; a first doped area having the first conductivity disposed in the first doped well; a second doped area having a second conductivity disposed in the first doped well; and an epitaxial layer disposed in the substrate, wherein the epitaxial layer has a third doped area with the first conductivity and a fourth doped area with the second conductivity separated from each other. Whereby a first bipolar junction transistor (BJT) equivalent circuit is formed between the first doped area, the first doped well and the third doped area; a second BJT equivalent circuit is formed between the second doped area, the first doped well and the fourth doped area; and the first BJT equivalent circuit and the second BJT equivalent circuit have different majority carriers.Type: GrantFiled: February 9, 2012Date of Patent: February 24, 2015Assignee: United Microelectronics CorporationInventors: Chang-Tzu Wang, Tien-Hao Tang, Kuan-Cheng Su
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Patent number: 8956943Abstract: A method for manufacturing a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby forming a nitride layer on a sidewall of the gate conductive layer and extending into the opening.Type: GrantFiled: May 27, 2013Date of Patent: February 17, 2015Assignee: United Microelectronics CorporationInventors: Chien-Hung Chen, Tzu-Ping Chen, Yu-Jen Chang
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Patent number: 8946854Abstract: A metal-insulator-metal (MIM) capacitor structure includes a first dielectric layer, a first damascene electrode layer, an insulating barrier layer, a second dielectric layer and a second damascene electrode layer. The first damascene electrode layer is formed in the first dielectric layer. The insulating barrier layer covers the first dielectric layer and the first damascene electrode layer, and is a single layer structure. The second dielectric layer is formed on the insulating barrier layer. The second damascene electrode layer is formed in the second dielectric layer and is contacted with the insulating barrier layer. The MIM capacitor structure can includes a dual damascene structure formed in the second dielectric layer and the insulating barrier layer and electrically connected to the first damascene electrode layer. A method for manufacturing the MIM capacitor structure is also provided.Type: GrantFiled: November 9, 2011Date of Patent: February 3, 2015Assignee: United Microelectronics CorporationInventors: Ji Feng, Duan-Quan Liao, Hai-Long Gu, Ying-Tu Chen
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Patent number: 8921185Abstract: A method for fabricating an integrated circuit includes the following steps of: providing a substrate with at least one isolation structure formed therein so as to separate the substrate into a first active region with a first stacked structure formed thereon and a second active region with a second stacked structure formed thereon; forming an interlayer dielectric layer covering the first stacked structure and the second stacked structure; and planarizing the interlayer dielectric layer to expose the top surface of the first stacked structure, wherein the second stacked structure is still covered by the interlayer dielectric layer after planarizing.Type: GrantFiled: April 17, 2014Date of Patent: December 30, 2014Assignee: United Microelectronics CorporationInventors: Hsiang-Chen Lee, Ping-Chia Shih, Ke-Chi Chen, Chih-Ming Wang, Chi-Cheng Huang
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Patent number: 8917109Abstract: A pulse width estimation method, applied between an integrated circuit and a circuit system for generating a reference pulse with a predetermined pulse width, includes steps for the following: generating an under-test pulse with an under-test pulse width by the integrated circuit; delivering the under-test and reference pulses to the integrated circuit for multiplying the under-test pulse width and the predetermined pulse width thereof by a timing gain and thereby obtaining a gained under-test pulse and a gained reference pulse, respectively; providing, by the integrated circuit, a count pulse for sampling the gained under-test pulse and the gained reference pulse and thereby obtaining a first count number and a second count number, respectively; and estimating the under-test pulse width by using the predetermined pulse width, the first count number and the second count number. A pulse width estimation device is also provided.Type: GrantFiled: April 3, 2013Date of Patent: December 23, 2014Assignee: United Microelectronics CorporationInventors: Shi-Wen Chen, Yung-Hsiang Lin
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Patent number: 8896021Abstract: An integrated circuit device includes a semiconductor substrate and a first transistor and a second transistor constructed in the semiconductor substrate. The first transistor has a first operating voltage higher than a second operating voltage of a second transistor. The first transistor includes a first drain structure, a first source structure, an isolation structure and a first gate structure. The first source structure includes a high voltage first-polarity well region, a first-polarity body region, a heavily doped first-polarity region, a second-polarity grade region and a heavily doped second-polarity region. The heavily doped second-polarity region is surrounded by the second-polarity grade region. The second-polarity grade region is surrounded by the first-polarity body region. The second transistor includes a second drain structure, a second source structure, a second gate structure and a first-polarity drift region.Type: GrantFiled: September 14, 2011Date of Patent: November 25, 2014Assignee: United Microelectronics CorporationInventors: Chung-I Huang, Pao-An Chang, Ming-Tsung Lee
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Patent number: 8890250Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a first well region, a gate structure, a second well region, a second well region, a second conductive region, and a deep well region. The first well region contains first type conducting carriers. The second well region is disposed within the first well region, and contains second type conducting carriers. The first conductive region is disposed on the surface of the first well region, and contains the second type conducting carriers. The deep well region is disposed under the second well region and the first conductive region, and contacted with the second well region. The deep well region contains the second type conducting carriers.Type: GrantFiled: December 28, 2012Date of Patent: November 18, 2014Assignee: United Microelectronics CorporationInventors: Chang-Tzu Wang, Yu-Chun Chen, Tien-Hao Tang
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Patent number: 8877640Abstract: A cleaning solution is provided. The cleaning solution includes an aliphatic polycarboxylic acid, a chain sulfonic acid substantially less than 4 wt % and an amine containing buffer agent.Type: GrantFiled: March 21, 2013Date of Patent: November 4, 2014Assignee: United Microelectronics CorporationInventors: An-Chi Liu, Tien-Cheng Lan, Kuei-Hsuan Yu