Abstract: A wafer processing method includes: providing a wafer, wherein the wafer has a first position and a second position, and the first position faces the second position in a reference direction; coating a photoresist liquid on the wafer; and performing a heating process to heat the wafer coated with the photoresist liquid to form a photoresist layer on the wafer, wherein during the heating process, a temperature of the wafer gradually increases in the reference direction, so that a thickness of the photoresist layer gradually decreases in the reference direction.

Abstract: An image sensor structure includes a semiconductor substrate; an interconnection layer on the semiconductor substrate; nano-pillar structures, each including a first doped layer, a second doped layer and a third doped layer stacked in sequence; conductive structures, respectively electrically connected to the first doped layer and the interconnection layer, the second doped layer and the interconnection layer, and the third doped layer and the interconnection layer; a first insulating layer on the interconnection layer and wrapping the nano-pillar structures and the conductive structures, wherein the first doping layer is exposed on the first insulating layer; a transparent barrier layer on the first insulating layer; and a photoelectric thin film structure on the first insulating layer and electrically connected to the interconnection layer. The photoelectric thin film structure includes photoconductive film portions.

Abstract: A method for fabricating an inductor module includes steps of: providing a substrate; forming a first inter-level dielectric layer on the substrate; forming a plurality of second inter-level dielectric layers on the first inter-level dielectric layer; forming a trench penetrating at least two of the second inter-level dielectric layers; and forming a first metal layer in the trench.

Abstract: A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper passive component pattern, and the second layer includes a lower passive component pattern, wherein the upper passive component pattern is opposite to the lower passive component pattern. The first interconnection layer includes at least one first interconnect structure electrically connected on the upper passive component pattern. The second interconnection layer includes at least one second interconnect structure electrically connected on the passive component pattern. The first interconnect structure on the upper passive component pattern is hybrid bonded with the second interconnect structure on the lower passive component pattern. Therefore, the upper passive component pattern and the lower passive component pattern are joined by hybrid bonding to form a passive device.

Abstract: An OTP memory capacitor structure includes a semiconductor substrate, a bottom electrode, a capacitor insulating layer and a metal electrode stack structure. The bottom electrode is provided on the semiconductor substrate. The capacitor insulating layer is provided on the bottom electrode. The metal electrode stack structure includes a metal layer, an insulating sacrificial layer and a capping layer stacked in sequence. The metal layer is provided on the capacitor insulating layer and is used as a top electrode. The insulating sacrificial layer is provided between the metal layer and the capping layer. A manufacturing method of the OTP memory capacitor structure is also provided. By the provision of the insulating sacrificial layer, the bottom electrode formed first can be prevented from being damaged by subsequent etching and other processes, so that the OTP memory capacitor structure has better electrical characteristics.

Abstract: An NMOS structure includes a semiconductor substrate, a dielectric structure, a source doped region, a drain doped region, a channel region, a gate structure and two isolation P-type wells. The dielectric structure is formed in the semiconductor substrate to define an active region, in which the source/drain doped region and the channel region are formed. The channel region includes two opposite first sides and two opposite second sides. The source/drain doped region is respectively formed between the two second sides and the dielectric structure. The gate structure is formed on the semiconductor substrate. The gate structure covers a part of the dielectric structure beside the first sides. The two isolation P-type wells are formed in a part of the dielectric structure not covered by the gate structure. The isolation P-type wells respectively surround a periphery of the source/drain doped region and end at the respective second side.

Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.

Abstract: A semiconductor structure in which the upper and lower semiconductor wafers are bonded by a hybrid bonding method is provided. The two semiconductor wafers each have discontinuous multiple metal traces or spiral coil-shaped metal traces. By hybrid bonding the two semiconductor wafers, multiple discontinuous metal traces are bonded together to form an inductance element with a continuous and non-intersecting path, or the two spiral coil-shaped metal traces are bonded together to form an inductance element. In this semiconductor structure, the inductance element formed by hybrid bonding has the advantage that the inductance value is easily adjusted.

Abstract: An inductor module and a method for fabricating the same are disclosed. The inductor module includes a substrate, a first inter-level dielectric layer, a plurality of second inter-level dielectric layers, a trench, and a first metal layer. The first inter-level dielectric layer is disposed on the substrate. The second inter-level dielectric layers are sequentially stacked on the first inter-level dielectric layer. The trench is disposed to penetrate at least two of the second inter-level dielectric layers. The first metal layer is disposed in the trench. The first metal layer has a top side surface and a bottom side surface opposite to each other. The top side surface is coplanar with an upper surface of the trench in the second inter-level dielectric layers. The bottom side surface is coplanar with a bottom surface of the trench in the second inter-level dielectric layers.

Abstract: Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer.

Abstract: A method for fabricating flash memory is provided. A plurality of floating gate structures is formed on a gate dielectric layer in the memory device region of a substrate. The protective spacers are formed on two opposite sidewalls of each floating gate structure. A polysilicon gate structures are formed on the logic device region and a polysilicon control gate structure with an opening are formed on the memory device region to cover two adjacent floating gate structures, wherein the two protective spacers facing each other between two adjacent floating gate structures are exposed by the opening, and then the exposed protective spacer are removed. An ion implantation is performed on the substrate to form a source region between the two adjacent floating gate structures on each cell area. There will be no polysilicon material residue in the memory device region or pitting/undercutting phenomenon in the logic device region.

Abstract: A method for manufacturing semiconductor structure includes: providing a substrate having a first surface; forming a trench on the first surface, wherein a bottom surface and side walls of the substrate are configured along an outer periphery of the trench; annealing the substrate with high-purity argon or high-purity hydrogen to flatten the bottom surface and the side walls; conformally disposing a composite-material layer to cover the first surface, the bottom surface and the side walls; disposing a polysilicon material layer in the trench; removing the composite-material layer on the first surface; forming a multi-layer metal interconnection structure on the first surface and the polysilicon material layer, the multi-layer metal interconnection structure including a MEMS frame structure and through holes; removing the polysilicon material layer and the composite-material layer; using plasma treatment to the trench to flatten the bottom surface and the side walls. The plasma contains inert gas and hydrogen.

Abstract: A method for correcting a mask pattern includes: providing an original mask pattern including at least one dense pattern area and at least one isolated pattern area, and the original mask pattern being divided into a first pattern and a second pattern, wherein the first pattern is formed in the isolated pattern area and extends to the dense pattern area, and the second pattern is formed in the dense pattern area; forming at least one slot on at least one section of the first pattern, and the at least one section of the first pattern is located on at least one transition area between the at least one isolated pattern area and the at least one dense pattern area; and performing an optical proximity correction operation on the first pattern formed with at least one slot and the second pattern. Using the corrected mask pattern may avoid the occurrence of necking or breaking on portion of the post-transfer pattern.

Abstract: A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper electrode pattern, and the second layer includes a lower electrode pattern, wherein the upper electrode pattern is opposite to the lower electrode pattern. The first interconnection layer includes a plurality of first interconnect structures electrically connected on the upper electrode pattern. The second interconnection layer includes a plurality of second interconnect structures electrically connected on the lower electrode pattern. The first interconnect structures on the upper electrode pattern are hybrid bonded with the second interconnect structures on the lower electrode pattern. Therefore, the upper electrode patterns and the lower electrode patterns are joined by hybrid bonding to form a capacitor element.

Abstract: A new method for fabricating a semiconductor device with high selection phosphoric acid solution and eliminating the step of oxide removal and thus reducing oxide loss to improve yield gain and cost saving.

Abstract: Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer.

Abstract: Exemplary metal line structure and manufacturing method for a trench are provided. In particular, the metal line structure includes a substrate, a target layer, a trench and a conductor line. The target layer is formed on the substrate. The trench is formed in the target layer and has a micro-trench formed at the bottom thereof. A depth of the micro-trench is not more than 50 angstroms. The conductor line is inlaid into the trench.

Abstract: Provided herein is a method for manufacturing a semiconductor device. A substrate including a MEMS region and a connection region thereon is provided; a dielectric layer disposed on the substrate in the connection region is provided; a poly-silicon layer disposed on the dielectric layer is provided, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer is provided; and a passivation layer covering the dielectric layer is provided, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer, and a conductive layer conformally covering the connection pad and the poly-silicon layer in the transition region is provided.

Abstract: The present invention provides a structure of a gas sensor, comprising: a support, having a front side, a back side opposite to the front side, a cell region, and a peripheral region circling the cell region; a cavity, formed on the back side of the support in the cell region; a heater, disposed on the front side of the support covering the cavity; a sensing element, disposed on the heater; and a sealing layer, formed on the back side of the support covering inside the cavity.

Abstract: Exemplary metal line structure and manufacturing method for a trench are provided. In particular, the metal line structure includes a substrate, a target layer, a trench and a conductor line. The target layer is formed on the substrate. The trench is formed in the target layer and has a micro-trench formed at the bottom thereof. A depth of the micro-trench is not more than 50 angstroms. The conductor line is inlaid into the trench.