Patents Assigned to United Microelectronics Corporation
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Patent number: 9865693Abstract: A semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge. Additionally, a method of manufacturing the semiconductor memory device is also provided.Type: GrantFiled: August 4, 2016Date of Patent: January 9, 2018Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Weichang Liu, Zhen Chen, Shen-De Wang, Wang Xiang, Wei Ta
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Patent number: 9852983Abstract: A fabricating method of an anti-fuse structure, comprising: providing a substrate having a first conductive plug and a second conductive plug separated from the first conductive plug; forming an amorphous silicon layer on the substrate, wherein a portion of the amorphous silicon layer overlapping the first conductive plug is defined as a first region, and a portion of the amorphous silicon layer overlapping the second conductive plug is defined as a second region; performing an implantation process to the first region and the second region, wherein the first region has a higher doping concentration than the second region; forming a titanium nitride layer on the amorphous silicon layer; and patterning the titanium nitride layer and the amorphous silicon layer.Type: GrantFiled: February 8, 2017Date of Patent: December 26, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventor: Dai Yang Lee
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Patent number: 9793105Abstract: The invention provides a fabricating method of a FinFET, comprising: providing a substrate having fin structures; depositing an dielectric layer on the substrate filling between the fin structures; forming recesses to reveal a portion of the fin structure by removing a portion of the dielectric layer; performing a cleaning process on using a cleaning solution selected from one of a first solution, consisting of dHF and H2O2, and a second solution, consisting of dHF and DIO3; forming a gate structure across on the fin structures; and forming a source/drain structure on the substrate at two lateral sides of the gate structure. The present invention also provides a fabricating method of a FinFET having an improved cleaning step using a cleaning solution having one of a third solution, consisting of dHF and DIO3, and a fourth solution, consisting of NH4OH and DIO3 before formation of the source/drain structure.Type: GrantFiled: August 2, 2016Date of Patent: October 17, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Chun-Wei Yu, Hsu Ting, Chueh-Yang Liu, Yu-Ren Wang, Kuang-Hsiu Chen, Yi-Liang Ye
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Patent number: 9780193Abstract: A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.Type: GrantFiled: October 27, 2015Date of Patent: October 3, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Chia-Lin Lu, Yu-Cheng Tung, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
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Publication number: 20170271153Abstract: The invention provides a method of epitaxial structure formation in a semiconductor, comprising: providing a substrate; performing a dry etch to form a first recess; after performing the dry etch, performing a SPM cleaning process on the substrate by using a nozzle spraying SPM solution with an angle greater than zero and less than 45 degrees relative to the substrate; after performing the SPM cleaning process, performing a wet etch to form a second recess; after performing the wet etch, performing a pre-epi cleaning process; and growing an epitaxial structure in the second recess.Type: ApplicationFiled: March 15, 2016Publication date: September 21, 2017Applicant: UNITED MICROELECTRONICS CORPORATIONInventor: TSUNG-HSUN TSAI
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Patent number: 9768017Abstract: The invention provides a method of epitaxial structure formation in a semiconductor, comprising: providing a substrate; performing a dry etch to form a first recess; after performing the dry etch, performing a SPM cleaning process on the substrate by using a nozzle spraying SPM solution with an angle greater than zero and less than 45 degrees relative to the substrate; after performing the SPM cleaning process, performing a wet etch to form a second recess; after performing the wet etch, performing a pre-epi cleaning process; and growing an epitaxial structure in the second recess.Type: GrantFiled: March 15, 2016Date of Patent: September 19, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventor: Tsung-Hsun Tsai
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Patent number: 9735015Abstract: A method of manufacturing a semiconductor structure, comprising: providing a preliminary structure having a first region and a second region and comprising a plurality of first trenches in the first region; forming a metal layer filling the first trenches covering on the preliminary structure, wherein the metal layer comprises a concave portion in the second region and the concave portion defines an opening; forming a metal nitride layer on the metal layer by an nitride treatment; and performing a planarization process to remove the metal nitride layer and a portion of the metal layer to expose the preliminary structure.Type: GrantFiled: December 5, 2016Date of Patent: August 15, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Kun Ju Li, Hsin Jung Liu, Wei-Chuan Tsai, Min-Chuan Tsai, Yi Han Liao, Chun-Tsen Lu, Chun-Lin Chen, Jui-Ming Yang, Kuo-Chin Hung
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Patent number: 9716165Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.Type: GrantFiled: June 21, 2016Date of Patent: July 25, 2017Assignee: United Microelectronics CorporationInventors: Yu-Ying Lin, Kuan Hsuan Ku, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu Lin, Chun Yao Yang, Yu-Ren Wang, Neng-Hui Yang
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Patent number: 9678530Abstract: An clock skew adjusting structure is provided. The clock skew adjusting structure includes a substrate, a wiring structure, a first active component and a second active component. The wiring structure includes at least a wiring layer and at least a via, the via is configured for different wiring layers to be electrically connected with each other. The first active component is formed on the substrate and configured for delivering a clock signal to the wiring structure. The second active component is formed on the substrate and electrically connected to the first active component through the wiring structure thus forming a timing path. The second active component receives the clock signal through the timing path.Type: GrantFiled: August 6, 2015Date of Patent: June 13, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventor: Chien-Hung Chen
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Patent number: 9660086Abstract: The present invention provides a fin-shaped field effect transistor (FinFET), comprises: a substrate having a fin structure; a plurality trenches formed on the fin structure with an alloy grown in the trenches; a gate structure on the fin structure perpendicular to an extending direction of the fin structure in-between the plurality of trenches; and an amorphous layer on a surface of the fin structure exposed by the gate structure and disposed in-between the gate structure and the alloy. The invention also provides a manufacturing method of a fin-shaped field effect transistor (FinFET).Type: GrantFiled: May 17, 2016Date of Patent: May 23, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Chun-Yu Chen, Chung-Ting Huang, Ming-Hua Chang, Tien-Chen Chan, Yen-Hsing Chen, Hsin-Chang Wu
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Patent number: 9640663Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The high-voltage FinFET device includes: at least one fin structure, a working gate, a shallow trench isolation structure, and a first dummy gate. The fin structure includes a first-type well region and a second-type well region adjacent to the first-type well region, and further includes a first part and a second part. A trench is disposed between the first part and the second part and disposed in the first-type well region. A drain doped layer is disposed on the first part which is disposed in the first-type well region, and a source doped layer is disposed on the second part which is disposed in the second-type well region. The working gate is disposed on the fin structure which is disposed in the first-type well region and in the second-type well region.Type: GrantFiled: December 29, 2014Date of Patent: May 2, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Tai-Ju Chen, Yi-Han Ye, Te-Chih Chen
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Patent number: 9634125Abstract: A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided.Type: GrantFiled: February 18, 2016Date of Patent: April 25, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Yen-Liang Wu, Chung-Fu Chang, Yu-Hsiang Hung, Ssu-I Fu, Wen-Jiun Shen, Man-Ling Lu, Chia-Jong Liu, Yi-Wei Chen
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Patent number: 9627210Abstract: A method of fabricating an electrostatic discharge protection structure includes the following steps. Firstly, a semiconductor substrate is provided. Plural isolation structures, a well region, a first conductive region and a second conductive region are formed in the semiconductor substrate. The well region contains first type conducting carriers. The first conductive region and the second conductive region contain second type conducting carriers. Then, a mask layer is formed on the surface of the semiconductor substrate, wherein a part of the first conductive region is exposed. Then, a first implantation process is performed to implant the second type conducting carriers into the well region by using the mask layer as an implantation mask, so that a portion of the first type conducting carriers of the well region is electrically neutralized and a first doped region is formed under the exposed part of the first conductive region.Type: GrantFiled: May 20, 2016Date of Patent: April 18, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Chang-Tzu Wang, Yu-Chun Chen, Tien-Hao Tang
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Patent number: 9576803Abstract: The present invention provides a method for metal gate work function tuning before contact formation in a fin-shaped field effect transistor (FinFET), where in the method comprises the following steps. (S1) providing a substrate having a metal gate structure on a side of the substrate, (S2) forming a titanium nitride (TiN) layer on the side of the substrate, and (S3) performing a gate annealing to tune work function of the metal gate structure.Type: GrantFiled: May 13, 2015Date of Patent: February 21, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Kuo-Chih Lai, Yang-Ju Lu, Ching-Yun Chang, Yen-Chen Chen, Shih-Min Chou, Yun Tzu Chang, Fang-Yi Liu, Hsiang-Chieh Yen, Nien-Ting Ho
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Patent number: 9577029Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for manufacturing the same. The method includes a step hereinafter. A 5-layered dual-dielectric structure is provided on a substrate. The 5-layered dual-dielectric structure includes a bottom metal layer, a first dielectric layer, an intermediate metal layer, a second dielectric layer and a top metal layer in order. The first dielectric layer and the second dielectric layer have different thicknesses.Type: GrantFiled: November 21, 2014Date of Patent: February 21, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Zhi-Biao Zhou, Shao-Hui Wu, Chi-Fa Ku
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Patent number: 9571079Abstract: An integrated circuit includes a signal generating unit, a signal monitoring unit and a processing unit. The signal generating unit is configured to generate a control signal. The signal monitoring unit is configured to receive the control signal and accordingly output a monitor signal. The processing unit is configured to receive the monitor signal. The control signal is adjusted until the monitor signal is located within a preset range. A signal monitoring method used with the integrated circuit and a signal monitoring method used with a plurality of transistors are also provided.Type: GrantFiled: November 11, 2015Date of Patent: February 14, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Yu-Yee Liow, Ya-Nan Mou, Yuan-Hui Chen, Shih-Chin Lin, Po-Hua Chen, Wen-Hong Hsu
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Patent number: 9570315Abstract: A method of an interfacial oxide layer formation comprises a plurality of steps. The step (S1) is to remove a native oxide layer from a surface of a substrate; the step (S2) is to form an oxide layer on a surface of a substrate by piranha solution (SPM); the step (S3) is to cleaning a surface of the oxide layer by standard clean 1 (SC1), and the step (S4) is to etch he oxide layer by a solution comprising diluted hydrogen fluoride (dHF) and ozonized pure water (DIO3).Type: GrantFiled: March 18, 2015Date of Patent: February 14, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Chueh-Yang Liu, Yi-Liang Ye, Ted Ming-Lang Guo, Yu-Ren Wang
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Patent number: 9530783Abstract: A method for manufacturing a non-volatile memory with SONOS memory cells, which includes steps of: providing a substrate; forming a first gate oxide layer and a first gate conductive layer onto the substrate; forming a MOS transistor gate by executing a photolithography process on the first gate conductive layer, and then forming an ONO structure on the substrate; and forming a second gate conductive layer on the ONO substrate, and then forming a NVM transistor gate by executing a photolithography process on the second gate conductive layer.Type: GrantFiled: June 3, 2015Date of Patent: December 27, 2016Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Sung-Bin Lin, Wen-Chung Chang
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Patent number: 9525037Abstract: A trench gate metal oxide semiconductor field effect transistor includes a substrate and a gate. The substrate has a trench. The trench is extended downwardly from a surface of the substrate. The gate includes an insertion portion and a symmetrical protrusion portion. The insertion portion is embedded in the trench. The symmetrical protrusion portion is symmetrically protruded over the surface of the substrate.Type: GrantFiled: June 29, 2015Date of Patent: December 20, 2016Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Chun-Hong Peng, Yu-Hsi Lai
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Patent number: 9508813Abstract: The present invention provides a transistor comprising a substrate having a surface; a first deep well region in the substrate; a second deep well region in the substrate, isolated from and encircling the first deep well region; a first well region in the substrate and on the first deep well region; two second well regions in the second deep well region and respectively at two opposite sides of the first well region; a source region in the first well region and adjacent to the surface; two drain regions in the two second well regions respectively and adjacent to the surface; two gate structures on the surface, wherein each of the two gate structures is between the source region and one of the drain regions respectively; and a guard ring in the substrate encircling the second deep well region, and on the periphery of the transistor.Type: GrantFiled: May 7, 2015Date of Patent: November 29, 2016Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Yen-Ming Chen, Chiuling Lee, Min-Hsuan Tsai, Zheng Hong Chen, Wei Hsuan Chang, Tseng-Hsun Liu