Abstract: A method for fabricating a semiconductor device comprises steps as follows: A first dummy gate having a first high-k gate insulator layer, a first composite sacrificial layer, and a first dummy gate electrode sequentially stacked on a substrate is firstly provided. The first dummy gate electrode is subsequently removed to expose the first composite sacrificial layer. The first composite sacrificial layer is then removed. Thereafter, a first work function layer is formed on the first high-k gate insulator layer, and a first metal gate electrode is formed on the first work function layer.

Abstract: An electrostatic discharge protection circuit is used in an integrated circuit with a first sub-circuit working with a first working voltage source and a second sub-circuit working with a second working voltage source lower than the first working voltage source. The electrostatic discharge protection circuit includes a first metal-oxide-semiconductor transistor of a first conductive type, having a drain thereof electrically connected to a pad of the integrated circuit, and gate, source and bulk thereof electrically connected to a bulk voltage; and a guard ring of the first conductive type, surrounding the first metal-oxide-semiconductor transistor of the first conductive type and coupled to the second working voltage source.

Abstract: A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.

Abstract: A chip stacking structure includes a first chip and a second chip. The first chip includes a surface having a first group of pads formed thereon, and the second chip includes a surface having a second group of pads formed thereon. The second group of pads is bonded onto the first group of pads to define a plurality of capillary passages extending in a same direction. The chip stacking structure further includes an underfill filling up interspaces between the first chip and the second chip. The chip stacking structure is capable of avoiding chip deformation and cracking during a bonding process.

Abstract: A metal-insulator-metal (MIM) capacitor structure includes a first dielectric layer, a first damascene electrode layer, an insulating barrier layer, a second dielectric layer and a second damascene electrode layer. The first damascene electrode layer is formed in the first dielectric layer. The insulating barrier layer covers the first dielectric layer and the first damascene electrode layer, and is a single layer structure. The second dielectric layer is formed on the insulating barrier layer. The second damascene electrode layer is formed in the second dielectric layer and is contacted with the insulating barrier layer. The MIM capacitor structure can includes a dual damascene structure formed in the second dielectric layer and the insulating barrier layer and electrically connected to the first damascene electrode layer. A method for manufacturing the MIM capacitor structure is also provided.

Abstract: A method for fabricating a high voltage semiconductor device is provided. Firstly, a substrate is provided, wherein the substrate has a first active zone and a second active zone. Then, a first ion implantation process is performed to dope the substrate by a first mask layer, thereby forming a first-polarity doped region at the two ends of the first active zone and a periphery of the second active zone. After the first mask layer is removed, a second ion implantation process is performed to dope the substrate by a second mask layer, thereby forming a second-polarity doped region at the two ends of the second active zone and a periphery of the first active zone. After the second mask layer is removed, a first gate conductor structure and a second gate conductor structure are formed over the middle segments of the first active zone and the second active zone, respectively.

Abstract: The present invention relates to a fabricating method of a semiconductor element. First, a substrate is provided and a first layout structure having a first width is formed on the substrate. Then, an etching mask is formed to cover the first layout structure, and the etching mask exposes a portion of the first layout structure. After that, the first layout structure is etched with the etching mask to form a second layout structure having a second width. The second width is less than the first width. This fabricating method is capable of finishing the fabrication of gate structures in two different directions. Accordingly, the layout flexibility is improved.

Abstract: An integrated circuit design and fabrication method includes the following steps. Firstly, an integrated circuit design layout is provided. Then, a first hotspot group and a second hotpot group are searched from the integrated circuit design layout. Then, a hotspot score is acquired according to the first hotspot group, the second hotpot group and a product functionality. If the hotspot score is higher than a criterion, the integrated circuit design layout is corrected according to the first hotspot group and the second hotpot group.

Abstract: A bond pad structure comprises an interconnection structure and an isolation layer. The dielectric layer has an opening and a metal pad. The isolation layer is disposed on the interconnection structure and extends into the opening until it is in contact with the metal pad, whereby the sidewalls of the opening is blanketed by the isolation layer, and a portion of the metal pad is exposed from the opening.

Abstract: An exemplary ESD protection device is adapted for a high-voltage tolerant I/O circuit and includes a stacked transistor and a gate-grounded transistor e.g., a non-lightly doped drain type gate-grounded transistor. The stacked transistor and the gate-grounded transistor are electrically coupled in parallel between an I/O pad and a grounding voltage of the high-voltage tolerant I/O circuit.

Abstract: A semiconductor device comprises a metal gate electrode, a passive device and a hard mask layer. The passive device has a poly-silicon element layer. The hard mask layer is disposed on the metal gate electrode and the passive electrode and has a first opening and a second opening substantially coplanar with each other, wherein the metal gate electrode and the poly-silicon element layer are respectively exposed via the first opening and the second opening; and there is a distance between the first opening and the metal gate electrode substantially less than the distance between the second opening and the poly-silicon element layer.

Abstract: A fin field-effect transistor structure comprises a substrate, a fin channel, a source/drain region, a high-k metal gate and a plurality of slot contact structures. The fin channel is formed on the substrate. The source/drain region is formed in the fin channel. The high-k metal gate formed on the substrate and the fin channel comprises a high-k dielectric layer and a metal gate layer, wherein the high-k dielectric layer is arranged between the metal gate layer and the fin channel. The slot contact structures are disposed at both sides of the metal gate.

Abstract: A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.

Abstract: A method of fabricating a MOS device comprises steps as follows: An interfacial layer, a high-k dielectric layer and a cover layer on a substrate are sequentially formed. Then an in-situ wet etching step is performed by sequentially using a first etching solution to etch the cover layer and using a second etching solution to etch the high-k dielectric layer and the interfacial layer until the substrate is exposed, wherein the second etching solution is a mixed etching solution containing the first etching solution.

Abstract: A bonding pad structure is used in an integrated circuit device. The integrated circuit device includes a semiconductor substrate with a first surface and a second surface. The bonding pad structure includes a dielectric layer, a conductor structure, a pad opening and an isolation trench. The dielectric layer is formed on the second surface of the semiconductor substrate. The conductor structure is disposed within the dielectric layer. The pad opening is formed in the first surface of the semiconductor substrate. The pad opening runs through the semiconductor substrate and a part of the dielectric layer, so that the conductor structure is exposed. The isolation trench has an opening in the first surface of the semiconductor substrate. The isolation trench runs through the semiconductor substrate and a part of the dielectric layer, and the isolation trench is disposed around the pad opening.

Abstract: A fabricating method of a semiconductor element includes the following steps. First, a substrate is provided. A metal gate structure and source/drain electrodes are already formed on the substrate. An amorphization process is performed in the source/drain electrodes to form an amorphous portion. An interlayer dielectric layer is formed on surfaces of the source/drain electrodes and a through hole contact is formed within the interlayer dielectric layer. A silicidation process is performed with the through hole contact and the amorphous portion of the source/drain electrodes to form a metal silicide layer. The fabricating method is capable of finishing the formation of the metal silicide layer in the condition that diameters of the through hole contact is becoming smaller and smaller.

Abstract: An image sensor comprises a substrate, a plurality of photoelectric transducer devices, an interconnect structure, at least one dielectric isolator and a back-side alignment mark. The substrate has a front-side surface and a back-side surface opposite to the front-side surface. The interconnect structure is disposed on the front-side surface. The photoelectric transducer devices are formed on the front-side surface. The dielectric isolator extends downwards into the substrate from the back-side surface in order to isolate the photoelectric transducer devices. The back-side alignment mark extends downwards into the substrate from the back-side surface and references to a front-side alignment mark previously formed on the front-side surface.

Abstract: A circuit structure of a test-key and a test method thereof are provided. The circuit structure comprises a plurality of transistors, a first conductive contact, a plurality of second conductive contacts and a plurality of third conductive contacts. The transistors are arranged in a matrix. The first conductive contact is electrically connected to one source/drain of each transistor in each column of the matrix. Each second conductive contact is electrically connected to the other source/drain of each transistor in a corresponding column of the matrix. Each third conductive contact is electrically connected to the gate of each transistor in a corresponding row of the matrix. In the method, a plurality of driving pulses are provided to the third conductive contacts in sequence, and a plurality of output signals are read from the second conductive contacts to perform an element-character analyzing operation when a row of the transistors is turned on.

Abstract: A chip stacking structure includes a first chip and a second chip. The first chip includes a surface having a first group of pads formed thereon, and the second chip includes a surface having a second group of pads formed thereon. The second group of pads is bonded onto the first group of pads to define a plurality of capillary passages extending in a same direction. The chip stacking structure further includes an underfill filling up interspaces between the first chip and the second chip. The chip stacking structure is capable of avoiding chip deformation and cracking during a bonding process.

Abstract: An integrated circuit device includes a semiconductor substrate and a first transistor and a second transistor constructed in the semiconductor substrate. The first transistor has a first operating voltage higher than a second operating voltage of a second transistor. The first transistor includes a first drain structure, a first source structure, an isolation structure and a first gate structure. The first source structure includes a high voltage first-polarity well region, a first-polarity body region, a heavily doped first-polarity region, a second-polarity grade region and a heavily doped second-polarity region. The heavily doped second-polarity region is surrounded by the second-polarity grade region. The second-polarity grade region is surrounded by the first-polarity body region. The second transistor includes a second drain structure, a second source structure, a second gate structure and a first-polarity drift region.