Abstract: A method of fabricating an opening with a deep ultra-violet photoresist layer. An insulating layer is formed on a substrate having a device structure. A deep ultra-violet photoresist layer with a first opening is formed on the insulating layer and a hard mask layer is then formed on the surface and the sidewalls of the deep ultra-violet photoresist layer. The first opening is used to pattern the insulating layer to form a second opening within the insulating layer wherein the hard mask layer is to protect the deep ultra-violet photoresist layer. The deep ultra-violet photoresist layer and the hard mask layer are removed to expose the insulating layer and a desired opening is thus accomplished.

Abstract: A method and a testing system for measuring contact resistance of a pin on an integrated circuit. An RC circuit is coupled to the integrated circuit, and a response signal of a testing signal input to the integrated circuit is monitored. The response signal has a time dependent voltage V′. Another time dependent voltage V1 for the testing signal through the RC circuit and a voltage drop across an internal circuit of the integrated circuit is illustrated. Comparing V′ with V1, whether the contact resistance of the pin being tested is allowable can be determined according to the ratings or specification of the integrated circuit.

Abstract: A method of testing a leakage current caused by a self-aligned silicide process is described. The invention uses different test structure to monitor degree of and reason for a leakage current caused by a self-aligned silicide process. While monitoring a self-aligned silicide process performed on a metal-oxide semiconductor transistor without a LDD region, in addition to considering a leakage current occurring from the metal silicide layer to the junction and occurring at edge of the metal silicide layer, the invention further considers a leakage current at comer of the metal silicide layer. For a metal-oxide semiconductor transistor having a LDD region, the invention further considers a leakage current from the metal silicide layer to the LDD region. The invention monitors a leakage current at comer of the metal silicide layer.

Abstract: A method for fabricating a landing pad is described in which a transistor is formed on the substrate, wherein the transistor comprises a gate and source/drain regions at both sides of the gate in the substrate. A cap layer and a spacer are formed on the gate and at the sidewall of the gate respectively. A protective layer is formed to cover the substrate. The protective layer is then defined to form an opening to expose the source/drain region. A polysilicon landing pad is then formed in the opening and on the protective layer at the periphery of the opening. Silicidation is then conducted on the polysilicon landing pad to form a metal silicide landing pad and to destroy any native oxide at the source/drain region.

Abstract: A vibration damper is described. A vibration damper with a high dampening ability is required for a scanner because of the requirement of the 0.18 &mgr;m size devices. The vibration damper is placed between a machine and a floor. The vibration damper has an I-shaped girder structure and a material filling the space between the floor and I-shaped girder structure. A support element having two layers of latticed armatures is mounted on the I-shaped girder structure. The support element is filled with cement. A layer of vibration absorber is placed on the cement.

Abstract: A method of fabricating a bit line of a flash memory. A silicon-on-insulator (SOI) has a buried oxide layer therein and a silicon layer thereon. A patterned hard mask layer is formed on the silicon layer. The exposed silicon layer and the buried oxide layer thereunder are removed to form a bit line opening while using the hard mask layer as a mask. A conformal lightly doped polysilicon layer is formed over the substrate. A heavily doped polysilicon layer is formed over the substrate and filling the bit line opening. The lightly doped polysilicon layer and the heavily doped polysilicon layer are removed until arriving at the silicon layer to form a bit line. The hard mask layer is then removed.

Abstract: A method for manufacturing a PMOS transistor. A gate terminal is formed over a substrate. Spacers are formed on the sidewalls of the gate terminal. A source/drain terminal is formed in the substrate on each side of the gate terminal, and then a metal silicide layer is formed over the top surface of the gate terminal and the substrate. The spacers are next removed. Using the metal silicide layer as a mask, a source/drain extension region is formed in the substrate between the gate terminal and the source/drain terminal. Similarly, using the metal silicide layer as a mask, an anti-punchthrough region is form in the substrate interior under the source/drain extension region.

Abstract: A method for manufacturing a shallow trench isolation. A substrate is provided, wherein the substrate has a pad oxide on the substrate and a silicon nitride layer on the pad oxide layer, and a trench penetrates through the silicon oxide layer and the pad oxide layer and into the substrate. A first oxide layer is conformally formed on the silicon nitride layer and in the trench. A rapid thermal process is performed. A second oxide layer is formed on the oxide layer to fill the trench. Portions of the first and the second oxide layers are removed to expose the silicon nitride layer.

Abstract: A fabrication process for a polysilicon gate is described in which a silicon dioxide layer of various thicknesses is formed on the substrate and on the polysilicon gate with an overlying anti-reflection layer. The silicon dioxide layer is removed with enough silicon dioxide layer remaining to cover the sidewalls of the polysilicon gate and the silicon substrate before the removal of the anti-reflection layer. The sidewalls of the polysilicon gate and the silicon substrate are thus simultaneously protected during the removal of the anti-reflection layer.

Abstract: A fabrication method for a gate spacer. The method comprises provision of a substrate with a gate formed thereon, after which a SiNx spacer is formed on the gate sidewall. The substrate is then covered with a SiOx layer. A part of the SiOx layer is removed until the surface of the SiOx layer is lower than the top surface of the gate. A portion of the SiNx layer is removed to expose the top edge of the gate spacer and to increase the exposed area of the gate. The SiOx layer is consequently removed.

Abstract: A damascene process is described. An opening is formed in a dielectric layer. The opening is filled with a conductive plug. The conductive plug is etched back to substantially reduce the thickness of the conductive plug in the dielectric layer. A conformal top barrier layer is formed over the conductive plug.

Abstract: A method for forming an insulating layer to solve a problem of non-uniform thickness of the insulating layer is provided. The method includes forming a first insulating layer over a substrate preferably by chemical vapor deposition (CVD) at an operation temperature of about 200° C.-350° C. The thickness of the first insulating layer is about 500 Å-5000 Å. A second insulating layer is formed over the first insulating layer preferably by CVD at a temperature of about 350° C.-500° C. The thickness of the second insulating layer is about 1000 Å-10000 Å. The first and the second insulating layers form together as an insulating layer to insulate transistors and isolation structures from the interconnect metal layer.

Abstract: A fabrication method for a vertical MOS device is described, in which dopants are implanted in the active region to form, from the bulk to the surface of the wafer respectively, a first doped layer, a second doped layer and a third doped layer. A portion of the isolation structure above the first doped layer is then removed, exposing the sidewalls of the second doped layer and the surface of the third doped layer but still concealing the first doped layer in the substrate. A gate oxide layer is further formed on the sidewalls of the second doped layer and the surface of the third doped layer. Furthermore, a conductive layer is formed at the second doped layer, covering the isolation structure, wherein the second doped layer and the conductive layer are isolated by the gate oxide layer.

Abstract: A method of forming interconnections is provided. A defined metal layer is formed as a metal line on a provided substrate. An oxide layer is formed on the metal layer and on the substrate. A silicon nitride layer is formed on the oxide layer. The oxide layer and the silicon nitride layer constitute a seed layer. A via hole is formed in the silicon nitride layer to expose the oxide layer positioned over the metal layer. A dielectric layer is formed on the seed layer. Since the silicon nitride layer and the oxide layer are different, a part of the dielectric layer positioned on the silicon nitride layer is a silicon oxide layer having holes therein. The other dielectric layer positioned on the oxide layer within the via hole is a dense silicon oxide layer.

Abstract: A method of fabricating a field effect transistor is described. A gate oxide layer is formed on a substrate. A gate is formed on the gate oxide layer. A source region and a drain region are formed beside the gate in the substrate. A first spacer is formed beside a sidewall of the gate. A preserve layer is formed beside the first spacer. A second spacer is formed beside a sidewall of the preserve layer.

Abstract: An apparatus and a method for performing chemical vapor deposition. The apparatus includes a plasma generator for dissociating source gases into atomic or ionic states, and a laminar flow reaction chamber connected to the plasma generator for depositing the dissociated atoms or ions. The apparatus and method utilizes the capacity of plasma to deposit thin films at a lower temperature combined with the capacity of a laminar flow chemical vapor deposition method to deposit a conformable layer.

Abstract: A method for fabricating a dielectric layer in an alignment marker area is provided. A wafer having an alignment marker area is formed. The alignment marker area has large trenches and small trenches formed in the wafer. A dielectric layer is formed over the wafer. Portions of the dielectric layer directly above the large trenches in the alignment marker area are removed to form trench structures.

Abstract: A method for forming shallow trench isolation region. The method includes the steps of forming spacers on the sidewalls of a patterned mask layer and a pad oxide layer, and then etching the substrate to form a trench using the mask layer and the spacers as a mask. Thereafter, a buffer layer conformal to the surface profile of the device is formed over the substrate, and then an insulation layer is formed inside the trench. The spacers can prevent the etching of the insulation layer to form recess cavities at the upper corners of the trench when the pad oxide layer is removed in an etching operation. Hence, the kink effect is prevented. The buffer layer can prevent the oxidation of trench sidewalls when the insulation layer is densified in an oxygen-filled atmosphere. Moreover, the buffer layer can also prevent sideways etching of the insulation layer when the pad oxide layer is etched.

Abstract: The structure in this present invention includes a substrate having a buried-in oxide layer near the surface of the substrate and a silicon surface layer of base over the buried-in oxide layer. After that the structure further includes a conductive layer of gate on the substrate, a dielectric layer on the conductive layer of gate, a metal plug penetrates through the conductive layer and the dielectric layer and reach down to the silicon surface layer but not through. The metal plug, the conductive layer of gate and the silicon surface of base are electrically coupled together.

Abstract: A fabrication method to increase the gate contact area is described, in which a conformal first sacrificial layer is formed on the silicon substrate and the gate structure. A second sacrificial layer is further formed on the silicon substrate, wherein the surface of the second sacrificial layer is lower than the top of the polysilicon gate by a certain thickness. The exposed sacrificial layer is then removed, followed by forming a conformal silicon layer to cover the silicon substrate. A spacer is further formed on a sidewall of the gate structure. Using the spacer as a mask, the exposed polysilicon layer is removed to form a side-wing polysilicon layer on both sides of the gate to increase the contact area of the gate. The spacer, the second sacrificial layer and the first sacrificial layer are then removed. A silicidation process is further conducted to form a silicide layer on the gate structure and the two side-wing polysilicon layer to lower the gate contact resistance.