Abstract: A salicide process is described. The edge of a gate are etched to form a reversed T-shaped gate that is then self-aligned by a silicide film. This etching step can be performed by using a silicon oxynitride layer as an etching mask over the gate.

Abstract: A method of manufacturing embedded DRAM whose DRAM gate is formed from a tungsten silicide layer and a polysilicon layer and whose logic gate is formed from a self-aligned silicide layer and a polysilicon layer. Moreover, the polysilicon layer in the DRAM gate and the logic gate has different thickness. The method of forming embedded DRAM includes the steps of forming a DRAM gate pattern and a logic gate pattern on a first photoresist layer. Next, the underlying silicon nitride layer, tungsten silicide layer and the second polysilicon layer are etched to form a DRAM gate structure. Thereafter, a second photoresist layer is formed over the DRAM circuit region. Finally, using the remaining silicon nitride layer, tungsten silicide layer and second polysilicon layer as an etching mask, the exposed layers in the logic circuit region are etched to form a logic gate composed of the first polysilicon layer, only.

Abstract: A method of in-line temperature monitoring. At least two control wafers and a monitor wafer are provided. A sacrificial layer is formed on each control wafer and the monitor wafer. Ions are implanted under a predetermined condition in the sacrificial layers. Thermal processes are performed on the control wafers at a higher and the lower limit of a target temperature to enable ions to move partially from the sacrificial layer to the control wafers. The sacrificial layers on the control wafers are subsequently removed. The sheet resistance of the control wafers is measured to obtain a first and the second resistance value, which respectively correspond to the first and second temperatures. A wafer and a monitor wafer are provided. A thermal process is performed on the monitor wafer and the wafer at the target temperature. The sacrificial layer of the monitor wafer is removed, and the sheet resistance of the monitor wafer is subsequently measured.

Abstract: A method for preventing the diffusion of dopants in a dual gate device includes the steps of providing a semiconductor substrate having wells and isolating structures thereon, and then forming a gate oxide layer over the well regions. Thereafter a polysilicon layer is formed over the gate oxide layer, and then a first conductive layer is formed over the polysilicon layer. Subsequently, a plasma treatment using gaseous nitrogen or gaseous ammonia is conducted to form a barrier layer. Finally, a second conductive layer is formed over the barrier layer.

Abstract: A sense/output circuit is designed for use with a memory device, such as an SDRAM (Synchronized Dynamic Random-Access Memory) device, which is capable of switching off some power-consuming circuit components immediately after the requested data output is completed. This feature can help reduce the power consumption by the overall memory system, making the use of the SDRAM device more cost-effective. Moreover, the reduction of power consumption can be achieved without concerning process parameters, component parameters, and temperature variations. As a result, the delay margin can be reduced compared to the prior art, which also contribute to the reduction of power consumption.

Abstract: A method for etching. The etching process is to form an opening within the material layer on the substrate and then form a patterned layer on the material layer. An etching gas, an inert gas/hydrogen and an inert gas are pumped into the chamber. The inert gas is used to decrease the surface temperature of the patterned layer and a polymer thin film layer can be formed easily on the surface of the patterned layer. The opening is then formed by defining the material layer with the patterned layer. In addition, the thin film can not be formed on the bottom of the opening by raising the temperature of the substrate.

Abstract: A method of water mark inspection. By forming a pattern on a test wafer, the water mark formed thereon directly reflects the features of a wafer product to be evaluated. The water mark is formed by simulating fabrication process conditions of forming the wafer product of which the performance is to be evaluated. Thus, after scanning the water mark by a defect inspection machine, the performance of the wafer product is evaluated.

Abstract: A method for manufacturing a charge storage electrode that utilizes the tendency for implanted phosphorus ions in a hemispherical grain (HSG) polysilicon layer to gather near the grooves so that the rate of oxidation there increases. Utilizing this property, a solution including an oxidizing agent and an etching agent mixed in a specified ratio is employed to etch the hemispherical grained polysilicon layer so that the grooves in the hemispherical polysilicon layer is deepened. Therefore, the surface area of the charge storage electrode is increased, and hence capacitance of the charge storage structure becomes greater. Moreover, the method used in this invention is compatible with the conventional processes and can be produced in batches. Therefore, production cost is low.

Abstract: A voltage regulator capable of improving system response. The voltage regulator includes a feedback circuit and an operational amplifier. The input terminal of the feedback circuit is coupled to an output voltage terminal for attenuating signals coming out of the output terminal. The operational amplifier comprises a pre-amplifier, a clamping circuit and a power amplifier, all serially connected together. The input terminals of the pre-amplifier are respectively coupled to the output terminal of the feedback circuit and an input voltage terminal. The pre-amplifier is a device for amplifying differential voltage between input voltage signals and feedback voltage signals. The clamping circuit is a device for clamping amplified differential voltage from the pre-amplifier between a pre-defined voltage range. The power amplifier is a device for increasing the power of the differential voltage signals.

Abstract: A method is provided for use in a semiconductor fabrication process to form buried diffusion junctions in conjunction with shallow-trench isolation (STI) structures in a semiconductor device. This method features beak-like oxide layers formed to serve as a mask prior to the forming of the STI structures, which can prevent the subsequently formed buried diffusion junctions from being broken up during the process for forming the STI structures. Moreover, sidewall-spacer structures are formed on the sidewalls of a silicon nitride layer used as a mask in the ion-implantation process. This can prevent short-circuits between the buried diffusion junctions when the doped areas are annealed to be transformed into the desired buried diffusion junctions.

Abstract: A structure of a memory cell in a memory device is taking an interface between a silicon nitride layer and a oxide layer. The memory cell includes: a polysilicon layer on a substrate, a silicon nitride layer on the polysilicon layer, an oxide layer on the silicon nitride layer, and a conductor layer on the oxide layer. The order of forming the silicon nitride layer and the oxide layer can be reversed either for another alternative structure of the memory cell.

Abstract: A method of manufacturing a shallow trench isolation alignment mark comprises the steps of first providing a silicon wafer whose surface has an alignment mark formed thereon. Next, a silicon nitride layer is formed over the silicon wafer, and then shallow trenches are formed. At least one of the shallow trenches is positioned at a distance of about 2000 .ANG. to 10000 .ANG. from the edge of the alignment mark. Thereafter, an oxide layer is formed over the silicon nitride layer, and then a chemical-mechanical polishing operation is conducted to remove a portion of the oxide layer and silicon nitride layer above the alignment mark. Altogether, a layer of silicon nitride having a thickness of about 600 .ANG. is removed from the top of the alignment mark. Finally, the silicon nitride layer is also removed. By forming a shallow trench at a distance of between 2000 .ANG. to 10000 .ANG.

Abstract: A method of fabricating cylindrical capacitors comprising the steps of forming a gate and a source/drain region on a substrate, and then forming an insulating layer over the substrate. Next, a contact opening that exposes one of the source/drain regions is formed in the insulating layer. Subsequently, a first conductive layer is deposited over the insulating layer and into the contact opening, and then the first conductive layer is patterned. Thereafter, a first deep ultra-violet photoresist layer, a hard mask layer and a second deep ultra-violet photoresist layer are sequentially formed over the substrate structure. Next, the second deep ultra-violet photoresist layer is used as a mask to pattern the hard mask layer and the first deep ultra-violet photoresist layer. Ultimately, an opening that exposes a portion of the first conductive layer is formed. Then, the second deep ultra-violet photoresist layer is removed.

Abstract: A method of fabricating a metal gate includes forming a gate insulating layer on a provided substrate, forming a PVD titanium nitride layer on the gate insulating layer, forming a CVD titanium nitride layer on the PVD titanium nitride layer, and forming a CVD tungsten layer on the CVD titanium nitride layer. The CVD tungsten layer, the CVD titanium nitride layer, and the PVD titanium nitride layer are later patterned to form the metal gate.

Abstract: A fabricating method for a DRAM capacitor is provided. A DRAM is formed on a substrate, wherein a transistor has been formed. A first oxide layer is formed over the substrate and a contact window is formed on the first oxide layer to expose a source region of the transistor. Then, a bit line is formed in the contact window, wherein the bit line is connected to the source region of the transistor. A second oxide layer is formed on the bit line and the first oxide layer. Then, a third oxide layer is formed on the second oxide layer. A second contact window is further defined to expose a drain region of the transistor, wherein the drain region has a native oxide layer formed on it. Next, a first polysilicon film is formed on the exposed drain region of the second contact window. A high dosage implantation is used to remove the native oxide layer. Then, a second polysilicon layer is formed over the substrate. Finally, the finishing process followed is performed to complete the fabrication of a DRAM capacitor.

Abstract: A method for manufacturing the capacitor of a dynamic random access memory cell. The method includes the steps of first providing a substrate having field effect transistors thereon, and then forming a dielectric layer over the substrate. Next, a contact opening that exposes the source/drain region is formed in the dielectric layer, and then conductive material is deposited over the substrate, filling the contact opening to form a conductive layer. Thereafter, the conductive layer is patterned, and then a portion of the exposed dielectric layer is removed to form trenches that surround the conductive layer. In the subsequent step, conductive spacers are formed on the sidewalls of the trenches and the conductive layer. The conductive spacers and the conductive layer form the lower electrode structure of a capacitor.

Abstract: A method and an apparatus of uninterrupted slurry supply. A plurality of polishers are provided. A slurry supply system comprises a slurry supply source, a plurality of valve boxes having a corresponding number as the polishers, a plurality of pipes to connect the valve boxes and the slurry supply source and the valve boxes and the polishers, a plurality of bypasses to connect between an inlet and an outlet of each of the valve boxes, and a plurality elbow type manually controlled three-way valve at a plurality of joints of the pipes and the bypasses. A slurry is supplied from the slurry supply source. A flowing direction of the slurry is selected by adjusting the three-way valve to supply the polishers for polishing.

Abstract: A fabrication method for a sharp tip emitter first includes a trench formed on a semiconductor substrate. Next, an isolating layer is deposited over the substrate by high-density plasma chemical vapor deposition (HDP CVD). A V-shaped groove is naturally formed on the isolating layer around the trench. Next, a silicon layer is formed over the isolating layer and an ion implantation is performed into the silicon layer over the V-shaped groove. Next, a semiconductor layer is formed over the substrate. Next, a high temperature thermal process is performed to drive the implanted ions into the semiconductor layer. Next, the isolating layer is removed so that the silicon layer is separated from the substrate. Then, the tip emitter is formed.

Abstract: A method of fabricating a shallow trench isolation. On a substrate comprising a pad oxide layer and a mask layer on the pad oxide layer, a trench which penetrates through the mask layer, the pad oxide layer, and a part of the substrate is formed. A part of the mask layer is removed to form an opening on top of the trench, wherein the opening is wider than the trench. An insulation layer is formed on the mask layer to fill the opening and the trench. The insulation layer is etched until the mask layer is exposed. The mask layer is removed, so that a T-shape insulation plug is formed. The insulation plug and the pad oxide layer are etched until the insulation plug and the substrate are at a same level.

Abstract: A method for manufacturing a charge storage electrode that utilizes the tendency for implanted phosphorus ions in a hemispherical grain (HSG) polysilicon layer to gather near the grooves so that the rate of oxidation there increases. Utilizing this property, a solution including an oxidizing agent and an etching agent mixed in a specified ratio is employed to etch the hemispherical grained polysilicon layer so that the grooves in the hemispherical polysilicon layer is deepened. Therefore, the surface area of the charge storage electrode is increased, and hence capacitance of the charge storage structure becomes greater. Moreover, the method used in this invention is compatible with the conventional processes and can be produced in batches. Therefore, production cost is low.