Abstract: A method for cleaning a semiconductor wafer which includes the sequential steps of cleaning the wafer in a dilute hydrofluoric acid bath, cleaning the wafer in a first ozone bath, cleaning the wafer in a dilute hydrofluoric acid/hydrogen peroxide/hydrogen chloride bath, followed by cleaning the wafer in a second ozone bath. The method uses the dilute hydrofluoric acid/hydrogen peroxide/hydrochloric acid bath instead of the conventional DHF bath and RCA2 bath. Hence, the amount of chemicals consumed and the number of baths used by the cleaning station are lowered. In addition, ozone is passed into an overflow loath so that the highly reactive ozone can be utilized to clean the wafer without putting additional load on the cleaning station. Therefore, the cleaning operation can be carried out in a smaller cleaning station using somewhat lower temperature and lower concentration chemical solutions. The efficiency is as high as a multi-bath station, but chemicals are not wasted.

Abstract: A method of defining the conductive layer is described in which a substrate comprises a dielectric layer and a conductive layer is formed covering the entire substrate. A common photolithography and etching process is conducted to form a wide trench pattern. An adjustment structure is also formed next to the sidewall on both sides of the trench such that the distance between the adjustment structures is same as the desired width of the conductive structure. After which, a cover layer is formed to fill the trench. Using the cover layer as a self-aligned hard mask, an anisotropic etching process is conducted to form a conductive structure.

Abstract: A dielectric layer in a dual-damascene interconnect is described. A dual-damascene interconnect structure is formed on a substrate. The dual-damascene interconnect structure has a first dielectric layer formed over the substrate, a second dielectric layer formed on the first dielectric layer, a first wire penetrating through the second dielectric layer and a second wire. The second wire penetrates through the second dielectric layer and is electrically coupled to the substrate. The second dielectric layer is removed. A barrier cap layer is formed conformally over the substrate. A third dielectric layer is formed on the barrier cap layer and an air gap is formed in a space enclosed by the third dielectric layer, the first and the second wires. A fourth dielectric layer is formed on the third dielectric layer. A planarizing process is performed to planarize the fourth dielectric layer.

Abstract: A method of manufacturing a cylindrical shaped capacitor includes the steps of providing a substrate that already has a polysilicon plug and a word line formed thereon, and then forming an insulation layer and a first dielectric layer over the substrate. Thereafter, the first dielectric layer is patterned to form an opening. Then, a first conductive layer and a second dielectric layer are deposited in sequence over the first dielectric layer and the opening. Next, the first conductive layer and the second dielectric layer are etched back to form spacers on the sidewalls of the opening. Subsequently, etching is carried out down through the opening using the sidewall spacers as a mask until the polysilicon plug is exposed. After that, a second conductive layer is formed over entire substrate, and then the second conductive layer is etched back so that only a portion of the second conductive layer and the first conductive layer remain.

Abstract: A method for fabricating a dual damascene structure is provided. The method contains providing a substrate, which has a patterned metal layer on it. A first liner oxide layer, a first seed layer are sequentially formed over the substrate. The first seed layer is patterned to form a first opening above the patterned metal layer to expose the first liner oxide layer. A first dielectric layer is formed over the substrate. The first dielectric layer includes a first porous dielectric layer on the first seed layer, and a first normal dielectric layer on the exposed portion of the first liner oxide layer. A first cap layer is formed over the first dielectric layer, and is planarized. An etching stop layer with a second opening above the first opening to expose the first cap layer is formed on the first cap layer.

Abstract: A method for recycling monitoring control wafers includes cleaning the wafers after performing a sheet resistance (Rs) measurement on a bare silicon monitoring control wafer of an ion implanter, and then converting the wafer into a recyclable control wafer. A recyclable control wafer for a thermal wave (TW) measurement of destruction can be obtained by forming a screen layer on the wafer, performing a TW measurement, performing ion implantation by the monitoring recipe, performing TW measurement again, performing ion drive-in to drive implanted ions into the deeper areas of the substrate, removing the screen layer, and then forming another screen layer on the wafer to put the wafer into the recycling process of a TW measurement.

Abstract: A method of fabricating a deep UV implantation mask. A deep UV photo-resist layer is formed on a substrate. The deep UV photo-resist layer is defined to cover a part of the substrate. A silylation process is performed to transform the surface of the deep UV photo-resist layer into a hard mask layer. Using the hard mask layer as a mask, the substrate is implanted with ions.

Abstract: A semiconductor memory device including a fast write recovery circuit. The semiconductor memory device has a memory array, a sense amplifier and the fast write recovery circuit. Before the end of a precharging operation, a last bit of data is written into a memory cell of the memory by the sense amplifier, as well as by the fast write recovery circuit from the other end. Thus, the time required for writing the last bit of data is shortened to prevent from writing a fragmental data into the memory cell in a transient write cycle. Furthermore, a write operation with a high speed can be executed with being restricted by layout.

Abstract: A method of forming buried bit lines. A silicon-on-insulator (SOI) substrate includes a silicon base layer, a first insulation layer and an epitaxial silicon layer. A shallow trench isolation (STI) layer that contacts the first insulation layer is formed in the epitaxial silicon layer. A trench that penetrates the STI layer and runs deep into the first insulation layer is formed. A buried bit line is formed inside the trench such that the top surface of the buried bit line is located between the upper and the lower surface of the STI layer. A second insulation layer is next formed over the buried bit line such that the top surface of the second insulation layer is at the same level as the top surface of the epitaxial silicon layer. A plurality of word lines and a plurality of source/drain regions are formed over the substrate and in the epitaxial silicon layer.

Abstract: A method of removing a copper oxide layer within a via hole. A copper layer is formed. A dielectric layer is formed on the copper layer. A via hole is formed to penetrate through the dielectric layer and expose a part of the copper layer within the via hole. The exposed copper layer reacts with oxygen in air to form a copper oxide layer. Using 1,1,1,5,5,5-hexafluoro-2,4-pentanedione, the copper oxide layer is removed.

Abstract: A method is proposed for eliminating signal skew in an SDRAM (Synchronized Dynamic Random-Access Memory) device resulting from the data signal being attenuated into different input signal amplitudes at the respective input points into the memory cells in the SDRAM device. The method is intended for use on a SDRAM device having at least a first memory cell and a second memory cell which are connected to a common signal line which transmits a data signal to both the first and the second memory cells. Due to the data signal being gradually attenuated along the signal line, the input signal amplitudes at the respective input points into the first and second memory cells are different, which would otherwise cause signal skew.

Abstract: A method of fabricating metallization. A metal nitride layer is formed on the exposed surface of the metal layer. The metal nitride layer is used as a barrier layer to prevent short circuit, which is produced by metal diffusing into the inter-metal dielectrics. Therefore, the reliability of devices can be improved.

Abstract: A method for avoiding plasma damage. In a semiconductor substrate of a first conductive type, a second conductive type well is formed. While forming the second conductive well, a high-energy dopant is doped into the semiconductor substrate. The high energy makes a depletion region between the substrate and the well have defects. A leakage path is thus formed. The leakage path can direct any charged carriers coming from plasma to avoid accumulation of the charged carriers in the well. Thus, the electrical characteristics of the well or even the quality of gate oxide formed thereon is prevented from being degraded.

Abstract: A silicon-on-insulator metallic oxide semiconductor structure having a double implanted source region. By etching a trench contact window in the double implanted source region and then depositing a metal into the trench to form a metal plug, contact between the source terminal and the substrate is established. Consequently, floating body effect of a silicon-on-insulator device is prevented without having to provide additional surface area to accommodate the contact window.

Abstract: An method of fabricating a shallow trench isolation. A semiconductor substrate having pad oxide layer and a hard mask layer is provided. The pad oxide layer and the hard mask layer are defined to expose a part of the substrate. The exposed substrate is etched to form a trench therewithin. An isolation layer is formed to fill the trench. The isolation layer is planarized by chemical mechanical polishing with the hard mask layer as an stop layer, so that a micro-scratch is formed on a surface of the isolation within the trench. A sacrificial layer is formed on the isolation layer and the hard mask layer. The micro-scratch is thus filled with the sacrificial layer. Using the hard mask as an etch stop, the sacrificial layer is etched back. Since the etching rate of the sacrificial layer is the same as or lower than the isolation layer within the trench, the formation of the micro-scratch is suppressed during the etching back process.

Abstract: A method for accurately determining a time to clean a LPCVD system is disclosed, in which gas flow readings of the gas supplying source from a mass flow meter (MFM) are recorded during the depositing process. The gas flow volume of the gas supplying source read from the MFM decreases as the congestion in the vacuum route of the LPCVD system increases. Based on the established relationship, an accurate time for cleaning the LPCVD system can be determined, so as to avoid product defects due to an excessive deposition.

Abstract: A method of fabricating a semiconductor device using a Salicide process to increase the surface area of a polysilicon gate is described. First, a polysilicon layer is formed over a substrate. A mask layer with an opening is formed on the polysilicon layer. A mask spacer is formed on the sidewalls of the opening. Part of the polysilicon layer under the opening is removed with the mask spacer and the mask layer serving as a mask. An insulating layer is formed in the opening. The mask spacer and the mask layer are removed. The polysilicon layer that is not covered by the insulating layer is removed. The insulating layer is removed to expose the surface of the remaining polysilicon layer, wherein a groove is formed on the surface of the remaining polysilicon layer. Then a Salicide process is performed to form a metal silicide layer on the substrate and the remaining polysilicon layer.

Abstract: A position detector is provided for use on a spin-drying machine employed in integrated circuit (IC) fabrication to detect whether the spin-drying machine has shifted in position during operation. If the spin-drying machine is positioned incorrectly, the position detector is capable of stopping the operation of robot arms used to grab and position wafers on the spin-drying machine so that the robot arms will not be damaged or crash into the wafers on the spin-drying machine due to the incorrect positioning of the spin-drying machine. The position detector is designed for use on a spin-drying machine having a spinning unit, a fixed platform surrounding the spinning unit, and at least one robot arm mounted on the fixed unit. The position detector comprises a pair of emitters mounted on the spinning unit and a pair of oppositely arranged receivers on the fixed platform.

Abstract: A low-dielectric constant insulation structure is described in which low-dielectric constant insulation layers and silicon oxide layers are alternately stacked on the substrate to form a stacked insulation layer. A required pattern is then etched in the stacked insulation layer followed by a selective etching to remove a portion of the low dielectric insulation layer to form, starting from the sidewall of the stacked insulation layer and extending inwardly, a plurality of recessed regions. A sputtering deposition and etching-back are further conducted on the sidewall of the stacked insulation layer to form a sidewall spacer to enclose the already formed recessed regions. A plurality of air-gaps is formed in the stacked insulation layer to establish a low dielectric insulation structure.

Abstract: A procedure for forming the barrier layer includes a plasma procedure in the fabricating procedure. The procedure is that an opening is formed on a dielectric layer, which is formed over a semiconductor substrate, by a damascene technology or a patterning process. Then, the plasma procedure is applied by following a procedure in which a halide gas is flowed over the substrate. Then, the halide gas is dissolved by applying plasma to it to form halogen atoms with free bonds, which can enter the dielectric layer to form another halide with the dielectric material and stay close to the surface. Then, a metal layer is formed over the substrate. The metal layer fills the opening and results in a reaction with the halide in the surface of the dielectric layer. A nonvolatile metallic halide layer, therefore, is formed. The nonvolatile metallic halide layer is a nonvolatile insulating layer that acts as the barrier layer between the metal layer and the dielectric layer.