Abstract: The present invention relates to a perovskite solar cell module and a manufacturing method for same. The perovskite solar cell module comprises a plurality of perovskite solar cells disposed on a substrate, each of the perovskite solar cells comprising: a first electrode, a first charge transport layer on the first electrode, an optical active layer formed of a perovskite crystal structure, and a second charge transport layer, which are laminated in this order; and a second electrode laminated on the second charge transport layer, wherein the second electrode included in each of the cells can be electrically connected in series to the first electrode of the closest perovskite solar cell and enhance the photoelectric conversion efficiency of the perovskite solar cell module.

Abstract: An apparatus for measuring round-trip time of a test signal using a programmable logic device comprises a pattern generator generating a test signal and measuring a round-trip time of the test signal, a programmable logic device of which internal circuits are configured to transmit the test signal in a predetermined manner, and bidirectional bus lines connecting the pattern generator and the programmable logic device. The round-trip time of the test signal is measured by a time difference between a starting time at which the pattern generator outputs the test signal and an arrival time at which the test signal is fed back to the pattern generator.

Abstract: The present invention relates to a sealed plasma melting furnace for treating low- and intermediate-level radioactive waste, which allows the secondary pollutants to be minimized.

Abstract: An apparatus for measuring round-trip time of a test signal using a programmable logic device comprises a pattern generator generating a test signal and measuring a round-trip time of the test signal, a programmable logic device of which internal circuits are configured to transmit the test signal in a predetermined manner, and bidirectional buses connecting the pattern generator and the programmable logic device. The round-trip time of the test signal is measured by a time difference between a starting time at which the pattern generator outputs the test signal and an arrival time at which the test signal is fed back to the pattern generator.

Abstract: A test board unit may include a test board, a thermal tank and a heat-dissipating plate. The test board may be configured to provide a semiconductor chip with a test current. The thermal tank may be configured to dissipate heat generated in the semiconductor chip. The heat-dissipating plate may be coupled between the test board and the thermal tank and may be configured to transfer the heat from the semiconductor chip to the thermal tank.

Abstract: A burn-in test system may include a burn-in test chamber, a heating chamber and a cooling chamber. The burn-in test chamber may receive an object thereon. The burn-in test chamber may perform a burn-in test at a burn-in test temperature. The heating chamber may be positioned at a first sidewall of the burn-in test chamber, and may preheat the object. The cooling chamber may be positioned at a second sidewall of the burn-in test chamber, and may cool the object.

Abstract: Disclosed is a detection system for detecting fail block using logic block address and data buffer address in a storage tester, which is capable of comparing data read from SSD test without expected data buffer. The system comprises a device driver for controlling HBA; a request processor for reading the request to Root Complex and transmitting the result to a data engine; and the data engine for generating data to be transmitted to SSD and comparing the read data.

Abstract: Disclosed is a device under test (DUT) tester using a redriver. The DUT tester more effectively tests the DUT, which is a predetermined semiconductor device, by applying an electrical signal to the DUT and measuring the electrical signal. The DUT tester includes a DUT test unit, a printed circuit board (PCB) provided therein with connectors for the connection with the DUT test unit, one DUT or more horizontally arranged on the PCB, and redrivers horizontally provided under the PCB and one-to-one matched with one DUT or more to compensate for the distortion of the signal integrity of test signals caused according to the variation of the transmission distance.

Abstract: Disclosed is a storage tester capable of individual control for a plurality of storages, which comprises a host terminal for receiving user's control signal for storage test; a communication interface unit transmitting data among the host terminal, an embedded processor and a data engine unit; a data engine unit for generating pattern data and command data and reading the data from the storage; a sequence control module for controlling respectively a plurality of SATA/SAS/PCIe interface units; and SATA/SAS/PCIe interface unit for connecting to the storage through one among SATA, SAS, PCIe interface according to the signal for interface selection generated from the embedded processor and controlling a plurality of storages according to control of the sequence control module by the embedded processor in order to test respectively connected storage.

Abstract: A system for test plural memories simultaneously includes a pattern generation part which generates a pattern signal for testing and transmits the signal to the memories, a delay part which receives data through a first data line from a first memory device that is disposed in a closest position from the delay part and a second data line from a second memory device that is disposed in a farthest position from the delay part, and a determination part which determines the result of testing by comparing the data from the first memory device and the second memory device. The delay part output the first data and the second data to the determination part simultaneously.

Abstract: A non-mounted storage test device based on FPGA includes a processor unit for performing enumeration and configuration for device, creating a scenario for test and performing test; a device driver unit for managing storage device; a data engine unit for generating pattern data for test and performing test; a system memory interface unit for receiving data for test and storing test result; a monitoring unit for monitoring packet; a DMA driver/address translation unit for performing DMA operation and transmitting Memory Read Request to Root Complex; a message input/output unit for transmitting to the data engine unit and the device driver unit; a switch unit for constituting DUT unit; a storage-in DUT unit as device under test which is storage for direct interface to PCIe including HBA; and a memory unit for storing data for test and record generated between tasks.

Abstract: An apparatus and method for acquiring data of fast fail memory includes a pattern generator for generating a pattern to be recorded to a device under test (DUT) and receiving DUT data from the DUT; a data transmitter for sending the DUT data and the pattern generated so as to correspond thereto to a failure analyzer from the pattern generator; and a failure analyzer for analyzing the DUT data and the pattern generated so as to correspond to the DUT data, which are received from the data transmitter, thus producing failure analysis information. The data transmitter (FIFO) able to advance the failure analysis time allows failure analysis to be performed before completion of testing, thereby shortening the total failure analysis time and overcoming hardware limitations for failure analysis.

Abstract: Disclosed is a storage interface apparatus for a solid state drive (SSD) tester which allows a plurality of interfaces to share a single protocol in parts where the protocol is commonly used in a multiple interface for interfacing a storage. The storage interface apparatus for the solid state driver tester includes: a host terminal for receiving a test condition for testing a storage from a user; and a test control unit for generating a test pattern corresponding to the test condition to test the storage. The test control unit includes a storage interface unit for interfacing the storage, and the storage interface unit includes a plurality of interfaces that share a protocol in parts where the protocol is commonly used.

Abstract: An apparatus and method for correcting an output signal of an FPGA-based memory test device includes a clock generator for outputting clock signals having different phases; and a pattern generator for outputting an address signal, a data signal and a clock signal in response to the clock signals input from the clock generator, and correcting a timing of each of the output signals using flip flops for timing measurement. Wherein the address signal, the data signal and the clock signal, through a pattern generator, are implemented with a programmable logic such as FPGA, thereby shortening the correcting time without the use of an external delay device, and increasing accuracy of output timing of the signal for memory testing, ultimately enhancing performance (accuracy) of a memory tester.

Abstract: Disclosed is a solid state drive tester which reduces the size of the tester and easily changes a function without changing hardware (H/W) by implementing a plurality of devices for testing an SSD as one chip using a Field Programmable Gate Array (FPGA). The solid state drive tester includes: a host terminal receiving a test condition for testing a storage from a user; and a test control unit generating a test pattern corresponding to the test condition, adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, and storing fail data generated during the test in an internal memory. The test control unit is implemented by an FPGA to reduce the size of the tester and easily change a function without hardware.

Abstract: A failure detection apparatus for a solid state driver tester is provided. The failure detection apparatus includes a host terminal for receiving a test condition for testing a storage from a user and a test control unit for creating a test pattern according to the test condition or creating a test pattern at random, and adaptively selects an interface according to a type of the storage to be tested to test the storage with the test pattern. The test control unit includes a plurality of buffer memories for storing readout data of the storage, stores the readout data in the buffer memories in an interleaving manner, and endows comparison of the created test pattern and the readout data stored in the buffer memories with continuity to test the storage in real time.

Abstract: Disclosed is an error generating apparatus of a solid state drive tester. The error processing operation of the storage is tested by inserting errors into a specific instruction to be transmitted to the storage, and detecting the results of the error processing operation of the storage when testing the storage. The error generating apparatus includes a host terminal for receiving a test condition for a test of a storage from a user, and a test control unit for generating a test pattern according to the test condition or generating a test pattern randomly, generating error data used to test an error characteristic of the storage, and testing the storage based on the test pattern and a normal instruction or an error instruction which is formed by inserting the error data into the normal instruction.

Abstract: Disclosed is a lighting device for a street lamp, of which a structure is improved such that the diffusion degree of light may be effectively controlled by improving the directivity of a luminous element. To this end, the lighting device for a street lamp includes: a base member which is formed at an upper side of a street lamp body arranged above a ground surface; a plurality of luminous element units, which are comprised of at least one luminous element, and are arranged on the bottom surface of the base member; and a plurality of reflection units, which are arranged to be adjacent to the luminous element units, and are arranged mutually isolated from each other by a predetermined distance on the bottom surface of the base member to diffuse light radiated from the luminous element units in multiple directions.

Abstract: Disclosed is a solid state drive tester which divides the functions of generating and comparing test pattern data and Frame Information Structure (FIS) data with each other into each other to implement the functions as separate logics, so that entire test time is decreased by reducing load of a processor. The solid state drive tester includes a host terminal for receiving a test condition for testing a storage from a user, and a test control unit creating a test pattern corresponding to the test condition, and adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, wherein the test control unit is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time.

Abstract: Disclosed is a non-mounted storage test device based on FPGA, which comprises a processor unit for performing enumeration and configuration for device, creating a scenario for test and performing test; a device driver unit for managing storage device; a data engine unit for generating pattern data for test and performing test; a system memory interface unit for receiving data for test and storing test result; a monitoring unit for monitoring packet; a DMA driver/address translation unit for performing DMA operation and transmitting Memory Read Request to Root Complex; a message input/output unit for transmitting to the data engine unit and the device driver unit; a switch unit for constituting DUT unit; a storage-in DUT unit as device under test which is storage for direct interface to PCIe including HBA; and a memory unit for storing data for test and record generated between tasks.