Abstract: A method for manufacturing a cantilever structure of a probe card is disclosed. In accordance with the method of the present invention, a first sacrificial wafer is used as a mold to form a cantilever structure having various shapes, a microscopic pitch and a high aspect ratio. In accordance with the method of the present invention, a probe tip may be formed by using a second sacrificial substrate and a bonding.

Abstract: A method for forming a bump of a probe card is disclosed. In accordance with the method, a bump having a high aspect ratio for supporting a probe tip and a probe beam is formed using a semiconductor substrate as a mold eliminating a need for a photoresist film.

Abstract: An apparatus and a method for generating a test pattern data for testing a semiconductor device are disclosed. In accordance with and in particular to the apparatus and the method, a test pattern program is compiled by predicting a data operation to generate a test pattern data in an interleaved fashion, thereby eliminating a need for a developer of the test pattern program to analyze the data operation during a writing of a source code.

Abstract: A tester for testing a semiconductor device is disclosed. In accordance with the tester, a data is fetched using a data strobe signal transmitted from a DUT, thereby increasing an accuracy of the fetched data, securing a window for fetching a last portion of the data using a data strobe enable signal and efficiently compensating for a round trip delay of an expected data without using the deskew component.

Abstract: A tester for testing a semiconductor device is disclosed. In accordance with the tester of the present invention, the tester is configured to have different drive signal path and input/output signal path wherein the drive signal path has a fly-by structure, i.e. a daisy chain structure and the input/output signal path has a star-stub structure such that more DUTs may be tested simultaneously and an integrity of the signals is secured.

Abstract: A method for manufacturing a probe structure is wherein a disclosed. In accordance with method, two semiconductor substrates having different crystal directions are bonded and selectively etched utilizing an etch selectivity due to the different crystal directions to form a probe tip region and a probe beam region. A cantilever structure for a probe card is formed by filling the probe tip region and the probe beam region with a conductive material.

Abstract: A tester for testing a semiconductor device is disclosed. The tester for testing the semiconductor device employs a data selector for converting a logical test pattern data transmitted from a pattern generator into a physical test pattern data and an expected data based on the logical test pattern data, thereby generating various timings based on a time delay instead of using a plurality of clocks to improve a test efficiency and reduce a manufacturing cost.

Abstract: A method for manufacturing a probe structure of a probe card is disclosed. In accordance with the method of the present invention, a dual etching process of a silicon substrate or an etching process of an SOI substrates is carried out using a sidewall insulating film pattern as an etching mask to facilitate a formation of a bump and microscopic probe structure of the probe card.

Abstract: Disclosed is an algorithm pattern generator for testing a memory device. It has a configuration which can optimize a configuration of a memory tester including an address scrambling and a data scrambling in the memory tester for carrying out a test at a memory device module level or a component level.

Abstract: The present invention relates to a semiconductor test interface for interfacing a DUT (Device Under Test) to a pin card using a cable comprising a DUT board including one or more first connectors for electrically connecting one or more test sockets for mounting the DUT to the one or more cables, and a circuit wiring for electrically connecting the one or more test sockets to the one or more first connectors; and the one more cable including a second connector for an electrical connection to the one or more first connectors, and a third connector for an electrical connection to the pin card, wherein the one or more first connectors correspond to the one or more cables by 1:1. In accordance with the present invention, the manufacturing cost is reduced by simplifying the manufacturing process and the semiconductor test interface may easily correspond to the test of the different DUTs.

Abstract: The present invention relates to a probe card that a probe of the probe card is movable only in a vertical direction using a trench to improve a electrical or a mechanical characteristic and to automatically limit the vertical movement thereof within a predetermined range. A pitch may be reduced so as to correspond to a decreasing distance between pads. A flatness of a probe tip may be maintained within a few micrometers using a semiconductor manufacturing process. 32 simultaneous parallel testing is possible contrary to a convention probe card. A wafer level testing is possible, and time and cost for a wafer testing are reduced.