Abstract: A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.

Abstract: Combined memories in integrated circuits are described, including determining a first requirement for logic blocks, determining a second requirement for memory blocks including a vertical configuration for the memory blocks, and compiling a design for the integrated circuit using the first requirement and the second requirement. The memory blocks may include non-volatile two-terminal cross-point memory arrays. The non-volatile two-terminal cross-point memory arrays can be formed on top of a logic plane. The logic plane can be fabricated in a substrate. The non-volatile two-terminal cross-point memory arrays may be vertically stacked upon one another to form a plurality of memory planes. The memory planes can be portioned into sub-planes. One or more different memory types such as Flash, SRAM, DRAM, and ROM can be emulated by the plurality of memory planes and/or sub-planes. The non-volatile two-terminal cross-point memory arrays can include a plurality of two-terminal memory elements.

Abstract: Memory power management is described. A non-volatile memory array is provided, the array including separately controlled memory blocks. At least two charge pumps are coupled to the array, the charge pumps being configured to provide at least two voltages. Logic is configured to control how the voltages are delivered to the memory blocks.

Abstract: A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.

Abstract: A serial memory interface is described, including a memory array, a plurality of serial ports in data communication with the memory array, transferring data between the memory array and at least one of the plurality of serial ports, and a logic block that is configured to control access to the memory array by the plurality of serial ports, the logic block using the serial ports to transfer data between the memory array and at least one of the plurality of serial ports.

Abstract: Cross point array with fast access time. A cross point array is driven by drivers on a semiconductor substrate. The drivers for either a single-layer cross point array or for the bottom layer of a stacked cross point array can be positioned to improve access time. Specifically, if the x-direction drivers are positioned in the middle of the x-direction conductive array lines and the y-direction drivers are positioned in the middle of the y-direction conductive array lines, the access time will be improved.

Abstract: A memory using a mixed valence conductive oxides. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

Abstract: Providing a reference voltage to a cross point memory array. The invention is a cross point memory array and some peripheral circuitry that, when activated, provides a reference voltage to a cross point array. The peripheral circuitry can be activated before, after or during selection of a specific memory plug. If the peripheral circuitry is activated during selection, only the unselected conductive array lines should be brought to the reference voltage. Otherwise, all the conductive array lines can be brought to the reference voltage.

Abstract: A memory array with enhanced functionality is presented. Each cell in the array includes a pair of memory element electrodes. A read current across the pair of memory element electrodes is indicative of stored information and different write voltage levels across the pair of memory element electrodes are employed to store nonvolatile information. The array has at least one enhanced functionality portion that performs operations selected from the group consisting of reference, error correction, device specific storage, defect mapping tables, and redundancy.

Abstract: A cross point array and peripheral circuitry that accesses the cross point array. The peripheral circuitry receives a supply voltage of approximately 1.8 volts or less, generates voltages of a magnitude not more than approximately 3 volts, and senses current that is indicative of a nonvolatile memory state.

Abstract: A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.

Abstract: A memory including a memory element having islands is provided. The memory has address decoding circuitry and an array of memory plugs. The memory plugs include memory element that have island structures of a first material within the bulk of a second material. The island structures are typically nanoparticles. The memory plugs can be placed in a first resistive state at a first write voltage, placed in a second resistive state at a second write voltage, and have its resistive state determined at a read voltage.

Abstract: A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminals selected. Sharing logic over multiple layers allows driver sets to be reused.

Abstract: Non-volatile memory cell with a single semiconductor device per memory cell. The present invention generally allows for a plurality of memory cells to be formed on a semiconductor substrate that supports a semiconductor device. A multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a voltage pulse is formed above the substrate, generally at a very high temperature. While the layers fabricated between the substrate and the multi-resistive state material use materials that can withstand high temperature processing, the layers fabricated above the multi-resistive state material do not need to withstand high temperature processing.

Abstract: Non-volatile memory cell with a single semiconductor device per memory cell. The present invention generally allows for a plurality of memory cells to be formed on a semiconductor substrate that supports a semiconductor device. A multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a voltage pulse is formed above the substrate, generally at a very high temperature. While the layers fabricated between the substrate and the multi-resistive state material use materials that can withstand high temperature processing, the layers fabricated above the multi-resistive state material do not need to withstand high temperature processing.

Abstract: Cross point memory array using distinct voltages. The invention is a cross point memory array that applies a first select voltage on one conductive array line, a second select voltage on a second conductive array line, the two conductive array lines being uniquely defined. Additionally, an unselect voltage is applied to the unselected conductive array lines. The unselect voltage can be applied before, after or during the selection process. The unselect voltage can be approximately equal to the average of the first select voltage and the second select voltage.

Abstract: A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element that is sandwiched between the electrodes. The bottom electrode can be described as having a top face with a first surface area, the top electrode has a bottom face with a second surface area and the multi-resistive state element has a bottom face with a third surface area and a top face with a fourth surface area. The multi-resistive state element's bottom face is in contact with the bottom electrode's top face and the multi-resistive state element's top face is in contact with the top electrode's bottom face. Furthermore, the fourth surface area is not equal to the second surface area.

Abstract: A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element. The multi-resistive state element is sandwiched between the electrodes such that the top face of the bottom electrode is in contact with the multi-resistive state element's bottom face and the bottom face of the top electrode is in contact with the multi-resistive state element's top face. The bottom electrode, the top electrode and the multi-resistive state element all have sides that are adjacent to their faces. Furthermore, the sides are at least partially covered by a sidewall layer.

Abstract: A re-writable memory that uses resistive memory cell elements with non-linear IV characteristics is disclosed. Non-linearity is important in certain memory arrays to prevent unselected cells from being disturbed and to reduce the required current. Non-linearity refers to the ability of the element to block the majority of current up to a certain level, but then, once that level is reached, the element allows the majority of the current over and above that level to flow.

Abstract: Non-volatile memory cell with a single semiconductor device per memory cell. The present invention generally allows for a plurality of memory cells to be formed on a semiconductor substrate that supports a semiconductor device. A multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a voltage pulse is formed above the substrate, generally at a very high temperature. While the layers fabricated between the substrate and the multi-resistive state material use materials that can withstand high temperature processing, the layers fabricated above the multi-resistive state material do not need to withstand high temperature processing.