Abstract: A measuring current generation circuit coupled to a setting resistor is disclosed. The generation circuit includes a first measuring terminal, a second measuring terminal, a first transconductance amplifier, a second transconductance amplifier and an output circuit. The first transconductance amplifier has a first input terminal and a second input terminal. The first input terminal is coupled to one terminal of the setting resistor. The second input terminal is coupled to another terminal of the setting resistor and coupled to the first measuring terminal. The second transconductance amplifier has a third input terminal and a fourth input terminal. The output circuit is coupled to output terminals of the first transconductance amplifier and the second transconductance amplifier respectively and has a first output terminal and a second output terminal. The first output terminal is coupled to the first input terminal. The second output terminal is coupled to the second measuring terminal.

Abstract: Provided is a method of forming a trench gate MOSFET. A hard mask layer is formed on a substrate. The substrate is partially removed by using the hard mask layer as a mask, so as to form a trench in the substrate. A first insulating layer and a first conductive layer are formed in the lower portion of the trench. A sacrificial layer is formed on the side surface of the upper portion of the trench, and the sacrificial layer is connected to the hard mask layer. An interlayer insulating layer is formed on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present. A second insulating layer and a second conductive layer are formed in the upper portion of the trench. A trench gate MOSFET is further provided.

Abstract: The disclosure provides a power switching circuit. The power switching circuit includes a driving circuit, a determining circuit, a first power switch, and a second power switch. The driving circuit outputs a first driving signal and a second driving signal. The determining circuit is coupled to the driving circuit and outputs a control signal to the driving circuit. The first power switch is coupled to a first input voltage and receives the first driving signal. The second power switch is coupled to a second input voltage and receives the second driving signal. When the first power switch and the second power switch are switched, the second driving signal rises from a first level to a preset level, and the determining circuit controls the driving circuit to utilize the first driving signal to turn off the first power switch.

Abstract: A plus width modulation (PWM) signal generator is disclosed. The PWM signal generator includes a first signal generator providing a first signal, an output terminal, a first voltage generating circuit including connected to the first voltage generating circuit for providing a first present voltage according to the first signal, and a second voltage generating circuit connected to the first signal generator for providing a second present voltage according to the first signal. The first present voltage is earlier supplied to the output terminal than the second preset voltage, and after the first preset voltage continuously is provided for a period of preset time, the first voltage generating circuit stops providing the first preset voltage.

Abstract: Provided is a method of forming a trench gate MOSFET. A hard mask layer is formed on a substrate. The substrate is partially removed by using the hard mask layer as a mask, so as to form a trench in the substrate. A first insulating layer and a first conductive layer are formed in the lower portion of the trench. A sacrificial layer is formed on the side surface of the upper portion of the trench, and the sacrificial layer is connected to the hard mask layer. An interlayer insulating layer is formed on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present. A second insulating layer and a second conductive layer are formed in the upper portion of the trench. A trench gate MOSFET is further provided.

Abstract: A time signal generating circuit of a power converter and a control method thereof are provided. The time signal generating circuit includes a reference frequency generating circuit, an on-time circuit and a frequency tracking circuit. The reference frequency generating circuit provides a reference frequency signal. The on-time circuit provides an on-time signal according to a first reference signal and a second reference signal. The second reference signal is related to an output voltage of the power converter. The frequency tracking circuit is coupled to the reference frequency generating circuit and the on-time circuit, and compares frequencies of the reference frequency signal and the on-time signal within a default time to generate a tracking signal. The on-time circuit adjusts the second reference signal according to the tracking signal, so that the on-time circuit adjusts the frequency of the on-time signal.

Abstract: A power switch circuit is disclosed. The power switch circuit includes a switch circuit, a first current protection circuit, a second current protection circuit and a selection circuit. The switch circuit is coupled between an input terminal and an output terminal. The switch circuit includes a first sensing switch, a second sensing switch and a power switch. The first sensing switch, the second sensing switch and the power switch are the same cell. The first current protection circuit is coupled to the second sensing switch. The second current protection circuit is coupled to the first sensing switch. The selection circuit is coupled to the switch circuit, first current protection circuit and second current protection circuit. The selection circuit generates a selection signal according to an output voltage to selectively enable the first current protection circuit or second current protection circuit.

Abstract: A current sensing circuit is provided. The current sensing circuit includes an amplifier, an input resistor, a sensing resistor, and a feedback circuit. The amplifier has a first input terminal, a second input terminal, a third input terminal, and an output terminal. The input resistor is coupled between the first input terminal and the second input terminal of the amplifier. The sensing resistor is coupled between the second input terminal and the third input terminal of the amplifier. The feedback circuit is coupled between the first input terminal and the output terminal. When an input current flows through the sensing resistor, a voltage across the sensing resistor is equal to a voltage across the input resistor, and the feedback circuit correspondingly outputs a sensing voltage according to the input current.

Abstract: The disclosure provides a power conversion circuit with a multi-function pin and a multi-function setting method thereof. The multi-function pin is coupled to an external setting circuit. The power conversion circuit includes a first function circuit, a second function circuit, and a judging circuit. The first function circuit is coupled to the multi-function pin. The second function circuit is coupled to the multi-function pin. The judging circuit is coupled to the multi-function pin, the first function circuit, and the second function circuit. The judging circuit provides a setting current to the multi-function pin, so that the external setting circuit generates a voltage according to the setting current. The judging circuit judges the type of external setting circuit according to voltage so as to activate the first function circuit or the second function circuit accordingly.

Abstract: An output stage circuit of a power conversion circuit includes a first power switch, a driving circuit, a first current source, a second current source and a combining circuit. The first power switch is coupled to a second terminal of a bootstrap capacitor. The driving circuit is coupled to the first terminal of the bootstrap capacitor and the first power switch and provides a control signal to the first power switch. The first current source generates a first current according to the control signal. The second current source generates a second current according to a reference voltage which is a first voltage at the first terminal or a second voltage at the second terminal. The combining circuit, coupled to the driving circuit, the first current source and the second current source, generates a switch operation indicating signal to the driving circuit according to the first current and second current.

Abstract: A transient voltage suppression device including a substrate of a first conductivity type, a first well of a second conductivity type, a first anode, a first cathode, and a first trigger node is provided. The first well is disposed in the substrate. The first anode is disposed in the substrate outside the first well and includes a second doped region of the second conductivity type and a third doped region of the first conductivity type disposed between the second doped region and the first doped region. The first trigger node is disposed between the first anode and the first cathode, and includes a fourth region of the first conductivity type disposed in the substrate and a fifth doped region of the second conductivity type at least partially disposed in the first well and disposed between the fourth doped region and the third doped region.

Abstract: The present application proposes an over-voltage protection circuit for a USB Type-C connector. The USB Type-C connector has at least one input signal pin. The over-voltage protection circuit includes a control circuit, a voltage level shift circuit, and a system clamping circuit. The control circuit generates a control signal according to a bias voltage. The voltage level shift circuit is electrically connected to the at least one input signal pin and the control circuit, and arranged to receive the control signal and at least one input signal and the control signal from the at least one input signal pin, and regulate a voltage level of the at least one input signal according to the control signal. The system clamping circuit is electrically connected to the level shift circuit, and clamps the voltage level of the regulated input signal down to below a threshold.

Abstract: A dc-dc controller is provided. The dc-dc controller includes a current sensing pin, a zero-current comparator, a comparison circuit and a threshold adjustment circuit. The current sensing pin is coupled to an output stage to receive a current sensing signal related to the output current. The zero-current comparator is coupled to the current sensing pin, and receives the current sensing signal and a first preset value to provide a zero-current signal. The comparison circuit is coupled to the zero-current comparator and the current sensing pin, and compares the current sensing signal with a second preset value to provide an adjustment signal. The threshold adjustment circuit is coupled to the comparison circuit and the zero-current comparator, and generates the first preset value according to the adjustment signal.

Abstract: A power conversion circuit includes an error amplifying circuit, a first comparison circuit, a second comparison circuit and a control circuit. The error amplifying circuit provides an output signal. The first comparison circuit, coupled to the error amplifying circuit, receives the output signal and a ramp signal to generate a first comparison signal. The second comparison circuit receives an output voltage and a first reference voltage and provides a second comparison signal. The control circuit, coupled to the error amplifying circuit, the first comparison circuit and the second comparison circuit, provides a control signal to control the error amplifying circuit according to the first comparison signal, the second comparison signal and an enabling signal. In a first operation mode of error amplifying circuit, the output signal is an error amplifying signal. In a second operation mode of error amplifying circuit, the output signal is a second reference voltage.

Abstract: Provided is a semiconductor device with a diode and a silicon controlled rectifier (SCR) including a substrate having a first conductivity type, a well region having a second conductivity type, a first doped region having the first conductivity type, and a second doped region having the second conductivity type. The well region is disposed in the substrate. The first doped region is disposed in the substrate. The second doped region is disposed in the substrate. The well region and the first doped region form a first PN junction, the well region and the substrate form a second PN junction, and the substrate and the second doped region form a third junction. The first, second, and third PN junctions form the SCR, and the first doped region and the third PN junction form the diode.

Abstract: The disclosure provides a power switching circuit. The power switching circuit includes a driving circuit, a determining circuit, a first power switch, and a second power switch. The driving circuit outputs a first driving signal and a second driving signal. The determining circuit is coupled to the driving circuit and outputs a control signal to the driving circuit. The first power switch is coupled to a first input voltage and receives the first driving signal. The second power switch is coupled to a second input voltage and receives the second driving signal. When the first power switch and the second power switch are switched, the second driving signal rises from a first level to a preset level, and the determining circuit controls the driving circuit to utilize the first driving signal to turn off the first power switch.

Abstract: A driving circuit and a switch signal generation method are provided. The driving circuit receives a PWM signal and provides a first switch signal and a second switch signal. The driving circuit includes a logical signal circuit, a lower bridge dead time circuit and a lower bridge driving circuit. The logical signal circuit provides a first logical signal and a second logical signal according to the PWM signal. The lower bridge dead time circuit determines a leading edge of a lower bridge dead time signal according to the first logical signal and determines a trailing edge of lower bridge dead time signal according to a trailing edge of first switch signal. The lower bridge driving circuit determines a leading edge of second switch signal according to second logical signal and determines a trailing edge of second switch signal according to the trailing edge of lower bridge dead time signal.

Abstract: Provided is a transient voltage suppression device including a power supply terminal, a ground terminal, a Zener diode, a diode string, and an isolation device. The Zener diode is coupled between the power supply terminal and the ground terminal, and a node is between the Zener diode and the power supply terminal. The diode string has a first terminal, a second terminal, and an input/output (I/O) terminal. The second terminal is coupled to the ground terminal. The isolation device is coupled between the node and the first terminal. When an abnormal current flows through the isolation device and an energy of the abnormal current per unit time exceeds a preset value of the isolation device, the isolation device blocks a path of the abnormal current.

Abstract: Provided is an electrostatic discharge protection device including a first work area and a second work area. The first work area is configured to form a face-to-face connected diode string. The first work area includes a plurality of first sub-work areas. Each of the first sub-work areas includes a first doped region of a first conductivity type disposed in a substrate, a second doped region of a second conductivity type disposed in the substrate and surrounding the first doped region, and a third doped region of the second conductivity type disposed below the second doped region. The second work area is configured to form at least one diode. The second work area includes at least one second sub-work area. The second sub-work area includes a fourth doped region of the second conductivity type disposed in the substrate. Besides, the fourth doped region is electrically connected to the first doped region.

Abstract: A filter and an operating method thereof are provided. The filter includes a logic circuit, a power circuit and a filter circuit. The logic circuit provides a switching control signal. The power circuit is coupled to the logic circuit. The filter circuit is coupled to the power circuit and the logic circuit. The filter circuit includes an amplifier, a first capacitor and a first transistor. An output end of the amplifier is coupled to the logic circuit, and provides an output signal. The first capacitor is coupled between an input end and output end of the amplifier. The first transistor is connected in parallel with the first capacitor. A control end of the first transistor is coupled to the power circuit. The logic circuit provides a switching control signal to the power circuit according to the output signal. The power circuit supplies a control voltage to the first transistor according to the switching control signal.